UPI-41A/41AH/42/42AH USER’S MANUAL
Table 2-2 lists the internal conditions which are testable
and indicates the condition which will cause a jump. In
all cases, the destination address must be within the
page of program memory (256 locations) in which the
jump instruction occurs.
OSCILLATOR AND TIMING CIRCUITS
The UPI-41A/41AH/42/42AH’s internal timing gen-
eration is controlled by a self-contained oscillator and
timing circuit. A choice of crystal, L-C or external
clock can be used to derive the basic oscillator frequen-
cy.
The resident timing circuit consists of an oscillator, a
state counter and a cycle counter as illustrated in Fig-
ure 2-9. Figure 2-10 shows instruction cycle timing.
Oscillator
The on-board oscillator is a series resonant circuit with
a frequency range of 1 to 12.5 MHz depending on
which UPI is used. Refer to Table 1.1. Pins XTAL 1
and XTAL 2 are input and output (respectively) of a
high gain amplifier stage. A crystal or inductor and
capacitor connected between XTAL 1 and XTAL 2
provide the feedback and proper phase shift for oscilla-
tion. Recommended connections for crystal or L-C are
shown in Figure 2-11.
State Counter
The output of the oscillator is divided by 3 in the state
counter to generate a signal which defines the state
times of the machine.
Each instruction cycle consists of five states as illustrat-
ed in Figure 2-10 and Table 2-3. The overlap of address
and execution operations illustrated in Figure 2-10 al-
lows fast instruction execution.
Table 2-2. Conditional Branch Instructions
Device
Instruction Mnemonic
Jump Condition
Jump if:
Accumulator
JZ
addr
All bits zero
JNZ
addr
Any bit not zero
Accumulator bit
JBb
addr
Bit ‘‘b’’
e
1
Carry flag
JC
addr
Carry flag
e
1
JNC
addr
Carry flag
e
0
User flag
JFO
addr
F
0
flag
e
1
JF1
addr
F
1
flag
e
1
Timer flag
JTF
addr
Timer flag
e
1
Test Input 0
JT0
addr
T
0
e
1
JNT0
addr
T
0
e
0
Test Input 1
JT1
addr
T
1
e
1
JNT1
addr
T
1
e
0
Input Buffer flag
JNIBF
addr
IBF flag
e
0
Output Buffer flag
JOBF
addr
OBF flag
e
1
231318 – 13
231318 – 14
Figure 2-9. Oscillator Configuration
Figure 2-10. Instruction Cycle Timing
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