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UPI-41A/41AH/42/42AH USER’S MANUAL

OUTL Pp,A instruction is latched and remains un-
changed until it is rewritten. Input data is sampled at
the time the IN, A, Pp instruction is executed. There-
fore, input data must be present at the PORT until read
by an INput instruction. PORT 1 and 2 inputs are fully
TTL compatible and outputs will drive one standard
TTL load.

Circuit Configuration

The PORT 1 and 2 lines have a special output structure
(shown in Figure 2-18) that allows each line to serve as
an input, an output, or both, even though outputs are
statically latched.

Each line has a permanent high impedance pull-up (50
K

X

) which is sufficient to provide source current for a

TTL high level, yet can be pulled low by a standard
TTL gate drive. Whenever a ‘‘1’’ is written to a line, a
low impedance pull-up (250

X

) is switched in momen-

tarily (500 ns) to provide a fast transition from 0 to 1.
When a ‘‘0’’ is written to the line, a low impedance
pull-down (300

X

) is active to provide TTL current

sinking capability.

To use a particular PORT pin as an input, a logic ‘‘1’’
must first be written to that pin.

NOTE:

A RESET initializes all PORT pins to the high im-
pedance logic ‘‘1’’ state.

An external TTL device connected to the pin has suffi-
cient current sinking capability to pull-down the pin to
the low state. An IN A, Pp instruction will sample the
status of PORT pin and will input the proper logic
level. With no external input connected, the IN A,Pp
instruction inputs the previous output status.

This structure allows input and output information on
the same pin and also allows any mix of input and
output lines on the same port. However, when inputs
and outputs are mixed on one PORT, a PORT write
will cause the strong internal pull-ups to turn on at all
inputs. If a switch or other low impedance device is
connected to an input, a PORT write (‘‘1’’ to an input)
could cause current limits on internal lines to be ex-
ceeded. Figure 2-19 illustrates the recommended con-
nection when inputs and outputs are mixed on one
PORT.

The bidirectional port structure in combination with
the UPI-41A/41AH/42/42AH logical AND and OR
instructions provide an efficient means for handling sin-
gle line inputs and outputs within an 8-bit processor.

PORTS 4, 5, 6, and 7

By using an 8243 I/O expander, 16 additional I/O lines
can be connected to the UPI-41AH, 42AH and directly
addressed as 4-bit I/O ports using UPI-41AH, 42AH

231318 – 23

Figure 2-18. Quasi-Bidirectional Port Structure

23

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Summary of Contents for UPI- 41A

Page 1: ...October 1993 Microprocessor Peripherals UPI 41A 41AH 42 42AH User s Manual Order Number 231318 006 ...

Page 2: ...specification known as errata Other brands and names are the property of their respective owners Since publication of documents referenced in this document registration of the Pentium OverDrive and iCOMP trademarks has been issued to Intel Corporation Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order Copies of documents ...

Page 3: ...tor and Timing Circuits ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14 Interval Timer Event Counter ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 16 Test Inputs ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 17 Interrupts ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 18 CONTENTS PAGE Reset ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 19 Data Bus Buffer ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 20 System Interface ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21 Input Output Interface ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22 Ports 1 and 2...

Page 4: ......

Page 5: ...ter system which tends to limit the ben efit derived from the peripheral chip In the past intelligent peripherals were designed to handle very specialized tasks Separate chips were de signed for communication disciplines parallel I O keyboard encoding interval timing CRT control etc Yet in spite of the large number of devices available and the increased flexibility built into these chips there is ...

Page 6: ...as a test input which can be T1 functions as a test input that can be directly directly tested using conditional branching tested using conditional branching instructions It instructions It functions as the event timer input works as the event timer input under software under software control control It is used during sync mode to reset the instruction state to S1 and synchronize the internal cloc...

Page 7: ...ocated physi cally on the UPI 41A 41AH 42 42AH These reg isters are the Data Bus Buffer Input DBBIN Data Bus Buffer Output DBBOUT and Status STATUS registers The host processor may read data from DBBOUT or write commands and data into DBBIN The status of DBBOUT and DBBIN plus user defined status is supplied in STATUS The host may read STATUS at any time An interrupt to the UPI proces sor is automa...

Page 8: ...er and Jump if not zero For Bit Manipulation AND to A immediate data or Register OR to A immediate data or Register XOR to A immediate data or Register AND to Output Ports Accumulator OR to Output Ports Accumulator Jump Conditionally on any bit in A For BDC Arithmetic Decimal Adjust A Swap 4 bit Nibbles of A Exchange lower nibbles of A and Register Rotate A left or right with or without Carry For ...

Page 9: ... changes are needed the entire program can be erased using UV lamp and reprogrammed in about 20 minutes This means the 8741A 8742 can be used as a single chip breadboard for very complex interface and control problems After the 8741A 8742 is programmed it can be tested in the actual production level PC board and the actual functional environment Changes required during system debugging can be made...

Page 10: ...mware KBC and SCC for portable apps 82C42PE N P S Phoenix MultiKey 42G firmware Energy Efficient KBC solution 87C42 N P S 4K One Time Programmable Version UPI L42 The low voltage 3 3V version of the UPI C42 Device Package ROM OTP Comments 80L42 N P S 4K ROM Device 82L42PC N P S Phoenix MultiKey 42 firmware PS 2 style mouse support 82L42PD N P S Phoenix MultiKey 42L firmware KBC and SCC for portabl...

Page 11: ...ocessor This chapter provides a basic description of the UPI microcomputer and its system interface registers Un less otherwise noted the descriptions in this section ap ply to the 8741AH 8742AH with OTP EPROM mem ory the 8741A 8742 with UV erasable program mem ory and the 8041AH 8042AH These devices are so similar that they can be considered identical under most circumstances All functions descri...

Page 12: ...UPI 41A 41AH 42 42AH USER S MANUAL 231318 7 Figure 2 2 Pin Configuration 231318 8 Figure 2 3 Logic Symbol 8 ...

Page 13: ...a common data bus A0 9 I COMMAND DATA SELECT Address input used by the master processor to indicate whether byte transfer is data A0 e 0 or command A0 e 1 TEST 0 1 I TEST INPUTS Input pins can be directly tested using TEST 1 39 conditional branch instructions FREQUENCY REFERENCE TEST 1 T1 also functions as the event timer input under software control TEST0 T0 is used during PROM programming and ve...

Page 14: ...H internal bus such as a register or an I O port The result of an ALU operation can be transferred to the internal bus or back to the accumulator If an operation such as an ADD or ROTATE requires more than 8 bits the CARRY flag is used as an indica tor Likewise during decimal adjust and other BCD operations the AUXILIARY CARRY flag can be set and acted upon These flags are part of the Program Stat...

Page 15: ...uffer full IBF interrupt or a timer interrupt or when a jump or call instruction is encountered An IBF inter rupt if enabled will automatically transfer control to location 3 while a timer interrupt will transfer control to location 7 All conditional JUMP instructions and the indirect JUMP instruction are limited in range to the current 256 location page that is they alter PC bits 0 7 only If a co...

Page 16: ... 10 bit program counter and bits 4 7 of the program status word PSW are stored in two stack locations When control is returned to the main program via an RETR instruction the program counter and PSW bits 4 7 are restored Returning via an RET instruction does not restore the PSW bits however The program counter stack is addressed by three stack pointer bits in the PSW bits 0 2 Opera tion of the pro...

Page 17: ... 8 is used to store general information about program exe cution In addition to the 3 bit Stack Pointer discussed previously the PSW includes the following flags CY Ð Carry AC Ð Auxiliary Carry F0 Ð Flag 0 BS Ð Register Bank Select 231318 12 Figure 2 8 Program Status Word The Program Status Word PSW is actually a collec tion of flip flops located throughout the machine which are read or written as...

Page 18: ... inductor and capacitor connected between XTAL 1 and XTAL 2 provide the feedback and proper phase shift for oscilla tion Recommended connections for crystal or L C are shown in Figure 2 11 State Counter The output of the oscillator is divided by 3 in the state counter to generate a signal which defines the state times of the machine Each instruction cycle consists of five states as illustrat ed in...

Page 19: ...put Ð Ð Ð Ð Ð Instruction Program Counter Opcode Address Timer Data ORLD Pp A Fetch Increment Output Increment Output Ð Ð Ð Ð Ð Instruction Program Counter Opcode Address Timer Data Fetch Increment Sample Increment Ð Fetch Ð Update Ð Ð J Conditional Instruction Program Counter Condition Timer Immediate Data Program Counter MOV STS A Fetch Increment Ð Increment Update Instruction Program Counter Ti...

Page 20: ...onfigu ration An 8 bit register is used to count pulses from either the internal clock and prescaler or from an exter nal source The counter is presettable and readable with two MOV instructions which transfer the contents of the accumulator to the counter and vice versa i e MOV T A and MOV A T The counter is stopped by a RESET or STOP TCNT instruction and remains stopped until restarted either as...

Page 21: ...d using UPI 41A conditional branch instructions In the second mode of operation illustrated in Figure 2 13 the TEST 1 pin is used as an input to the internal 8 bit event counter The Start Counter STRT CNT instruction controls an internal switch which connects TEST 1 through an edge detector to the 8 bit internal counter Note that this instruction does not inhibit the testing of TEST 1 via conditio...

Page 22: ...IS I instruc tion The timer overflow interrupt is enabled and dis abled by the EN TNCTI and DIS TCNTI instructions respectively Figure 2 14 illustrates the internal interrupt logic An IBF interrupt request is generated whenever WR and CS are both low regardless of whether interrupts are enabled The interrupt request is cleared upon entering the IBF service routine only That is the DIS I instruc ti...

Page 23: ...s first preset to FFH and the EN TCNTI instruction is executed A timer over flow interrupt is generated by the first high to low tran sition of the TEST 1 input pin Also if an IBF interrupt occurs during servicing of the timer counter interrupt it will remain pending until the end of the service rou tine Host Interrupts And DMA If needed two external interrupts to the host system can be created us...

Page 24: ...ous to the external processor timing This allows the UPI software to han dle peripheral control tasks independent of the main processor while still maintaining a data interface with the master system Configuration Figure 2 16 illustrates the internal configuration of the DBB registers Data is stored in two 8 bit buffer regis ters DBBIN and DBBOUT DBBIN and DBBOUT may be accessed by the external pr...

Page 25: ...WR I O WRITE signal used to transfer data from the system bus to the UPI DBBIN register and set the F1 flag in the status register RD I O READ signal used to transfer data from the DBBOUT register or status register to the system data bus CS CHIP SELECT signal used to enable one 8041AH out of several connected to a common bus A0 Address input used to select either the 8 bit status register or DBBO...

Page 26: ...nterrupt is generated if enabled Command Write During any write Table 2 4 the state of the A0 input is latched into the status register in the F1 command data flag location This additional bit is used to signal whether DBBIN contents are command A0 e 1 or data A0 e 0 information INPUT OUTPUT INTERFACE The UPI 41A 41AH 42 42AH has 16 lines for input and output functions These I O lines are grouped ...

Page 27: ...ns to the high im pedance logic 1 state An external TTL device connected to the pin has suffi cient current sinking capability to pull down the pin to the low state An IN A Pp instruction will sample the status of PORT pin and will input the proper logic level With no external input connected the IN A Pp instruction inputs the previous output status This structure allows input and output informati...

Page 28: ...ersa The 8243 I O ports PORTS 4 5 6 and 7 provide more drive capability than the UPI 41A 41AH 42 42AH bidirectional ports The 8243 output is capable of driving about 5 standard TTL loads Multiple 8243 s can be connected to the PORT 2 inter face In normal operation only one of the 8243 s would be active at the time an Input or Output command is executed The upper half of PORT 2 is used to provide c...

Page 29: ...UPI 41A 41AH 42 42AH USER S MANUAL 231318 25 231318 26 Figure 2 20 8243 Expander Interface 231318 27 Figure 2 21 Multiple 8243 Expansion 25 ...

Page 30: ...stored in Program Memory can be loaded directly into the accumulator or the eight working reg isters Data can also be transferred directly between the accumulator and the on board timer counter the Status Register STS or the Program Status Word PSW Transfers to the STS register alter bits 4 7 only Transfers to the PSW alter machine status ac cordingly and provide a means of restoring status after ...

Page 31: ...ignate any of the 8 working registers as a counter and can effect a branch to any address within the current page of execution A special indirect jump instruction JMPP A allows the program to be vectored to any one of several differ ent locations based on the contents of the accumulator The contents of the accumulator point to a location in program memory which contains the jump address As an exam...

Page 32: ...rogram memory can be ANDed and ORed directly to PORTS 1 and 2 with the result remaining on the port This allows masks stored in program mem ory to be used to set or reset individual bits on the I O ports PORTS 1 and 2 are configured to allow input on a given pin by first writing a 1 to the pin Four additional 4 bit ports are available through the 8243 I O expander device The 8243 interfaces to the...

Page 33: ...gister 2 2 MOV Rr Move immediate to Ýdata data memory 2 2 MOV A PSW Move PSW to A 1 1 MOV PSW A Move A to PSW 1 1 XCH A Rr Exchange A and registers 1 1 XCH A Rr Exchange A and data memory 1 1 XCHD A Exchange digit of A Rr and register 1 1 Mnemonic Description Bytes Cycle DATA MOVES Continued MOVP A A Move to A from current page 1 2 MOVP3 A Move to A from page 3 1 2 A TIMER COUNTER MOV A T Read Tim...

Page 34: ...a Rr r e 0 1 Example ADDM MOV RO Ý47 MOVE 47 DECIMAL TO REG 0 ADD A RO ADD VALUE OF LOCATION 47 TO ACC ADD A Ýdata Add Immediate Data to Accumulator Opcode 0 0 0 0 0 0 1 1 d7 d6 d5 d4 d3 d2 d1 d0 This is a 2 cycle instruction The specified data is added to the accumulator Carry is affected A w A a data Example ADDID ADD A ÝADDER ADD VALUE OF SYMBOL ADDER TO ACC ADDC A Rr Add Carry and Register Con...

Page 35: ... content of the carry bit is added to accumulator location 0 Then the specified data is added to the accumulator Carry is affected A w A a data a C Example ADDC A Ý255 ADD CARRY AND 225 DEC TO ACC ANL A Rr Logical AND Accumulator With Register Mask Opcode 0 1 0 1 1 r2 r1 r0 Data in the accumulator is logically ANDed with the mask contained in working register r A w A AND Rr r e 0 7 Example ANDREG ...

Page 36: ...ly ANDed with an immediately specified mask Pp w Pp AND data p e 1 2 Note Bits 0 1 of the opcode are used to represent PORT 1 and PORT 2 If you are coding in binary rather than assembly language the mapping is as follows Bits p1 p0 Port 0 0 X 0 1 1 1 0 2 1 1 X Example ANDP2 ANL P2 ÝOF0H AND PORT 2 CONTENTS WITH MASK F0 HEX CLEAR P20 23 ANLD Pp A Logical AND Port 4 7 With Accumulator Mask Opcode 1 ...

Page 37: ...0 BEGADD MOV A R1 MOVE CONTENTS OF REG 1 TO ACC ADD A R2 ADD REG 2 TO ACC CALL SUBTOT CALL SUBROUTINE SUBTOT ADD A R3 ADD REG 3 TO ACC ADD A R4 ADD REG 4 TO ACC CALL SUBTOT CALL SUBROUTINE SUBTOT ADD A R5 ADD REG 5 TO ACC ADD A R6 ADD REG 6 TO ACC CALL SUBTOT CALL SUBROUTINE SUBTOT SUBTOT MOV R0 A MOVE CONTENTS OF ACC TO LOCATION ADDRESSED BY REG 0 INC R0 INCREMENT REG 0 RET RETURN TO MAIN PROGRAM...

Page 38: ...E MENTED TO 10010101 CPL C Complement Carry Bit Opcode 1 0 1 0 0 1 1 1 The setting of the carry bit is complemented one is changed to zero and zero is changed to one C w NOT C Example Set C to one current setting is unknown CT01 CLR C C IS CLEARED TO ZERO CPL C C IS SET TO ONE CPL F0 COMPLEMENT FLAG 0 Opcode 1 0 0 1 0 1 0 1 The setting of Flag 0 is complemented one is changed to zero and zero is c...

Page 39: ...IT 1 0 01H RESULT DEC A Decrement Accumulator Opcode 0 0 0 0 0 1 1 1 The contents of the accumulator are decremented by one A w A b 1 Example Decrement contents of data memory location 63 MOV R0 Ý3FH MOVE 3F HEX TO REG 0 MOV A R0 MOVE CONTENTS OF LOCATION 63 TO ACC DEC A DECREMENT ACC MOV R0 A MOVE CONTENTS OF ACC TO LOCATION 63 DEC Rr Decrement Register Opcode 1 1 0 0 1 r2 r1 r0 The contents of w...

Page 40: ...me page If the DJNZ instruction begins in location 255 of a page it will jump to a target address on the following page Otherwise it is limited to a jump within the current page Example Increment values in data memory locations 50 54 MOV R0 Ý50 MOVE 50 DEC TO ADDRESS REG 0 MOV R3 Ý05 MOVE 5 DEC TO COUNTER REG 3 INCRT INC R0 INCREMENT CONTENTS OF LOCATION ADDRESSED BY REG 0 INC R0 INCREMENT ADDRESS...

Page 41: ...IBF w 0 Example INDBB IN A DBB INPUT DBBIN CONTENTS TO ACCUMULATOR IN A Pp Input Port 1 2 Data to Accumulator Opcode 0 0 0 0 1 0 p1 p0 This is a 2 cycle instruction Data present on port p is transferred read to the accumulator A w Pp p e 1 2 see ANL instruction Example INP 12 IN A P1 INPUT PORT 1 CONTENTS TO ACC MOV R6 A MOVE ACC CONTENTS TO REG 6 IN A P2 INPUT PORT 2 CONTENTS TO ACC MOV R7 A MOVE...

Page 42: ...3 a2 a1 a0 This is a 2 cycle instruction Control passes to the specified address if accumulator bit b is set to one PC0 7 addr if b e 1 PC w PC a 2 if b e 0 Example JB4IS1 JB4 NEXT JUMP TO NEXT ROUTINE IF ACC BIT 4 e 1 JC address Jump If Carry Is Set Opcode 1 1 1 1 0 1 1 0 a7 a6 a5 a4 a3 a2 a1 a0 This is a 2 cycle instruction Control passes to the specified address if the carry bit is set to one P...

Page 43: ...ithin Page Opcode 1 0 1 1 0 0 1 1 This is a 2 cycle instruction The contents of the program memory location pointed to by the accumulator are substituted for the page portion of the program counter PC 0 7 PC0 7 w A Example Assume accumulator contains OFH JMPPAG JMPP A JMP TO ADDRESS STORED IN LOCATION 15 IN CURRENT PAGE JNC address Jump If Carry Is Not Set Opcode 1 1 1 0 0 1 1 0 a7 a6 a5 a4 a3 a2 ...

Page 44: ...umulator con tents are nonzero at the time this instruction is executed PC0 7 w addr if A i 0 Example JACCNO JNZ OABH JUMP TO LOCATION AB HEX IF ACC VALUE IS NONZERO JOBF Address Jump If Output Buffer Full Flag Is Set Opcode 1 0 0 0 0 1 1 0 a7 a6 a5 a4 a3 a2 a1 a0 This is a 2 cycle instruction Control passes to the specified address if the Output Buffer Full OBF flag is set e 1 at the time this in...

Page 45: ...f Accumulator Is Zero Opcode 1 1 0 0 0 1 1 0 a7 a6 a5 a4 a3 a2 a1 a0 This is a 2 cycle instruction Control passes to the specified address if the accumulator con tains all zeros at the time this instruction is executed PC0 7 w addr if A e 0 Example JACCO JZ OA3H JUMP TO LOCATION A3 HEX IF ACC VALUE IS ZERO MOV A Ýdata Move Immediate Data to Accumulator Opcode 0 0 1 0 0 0 1 1 d7 d6 d5 d4 d3 d2 d1 d...

Page 46: ... Timer Counter Contents to Accumulator Opcode 0 1 0 0 0 0 1 0 The contents of the timer event counter register are moved to the accumulator The timer event counter is not stopped A w T Example Jump to Exit routine when timer reaches 64 that is when bit 6 is setÐassuming initializa tion to zero TIMCHK MOV A T MOVE TIMER CONTENTS TO ACC JB6 EXIT JUMP TO EXIT IF ACC BIT 6 e 1 MOV PSW A Move Accumulat...

Page 47: ...HEX IS MOVED INTO REG 6 MOV Rr A Move Accumulator Contents to Data Memory Opcode 1 0 1 0 0 0 0 r The contents of the accumulator are moved to the data memory location whose address is specified by bits 0 7 of register r Register r contents are unaffected Rr w A r e 0 1 Example Assume R0 contains 11000111 MDMA MOV R A MOVE CONTENTS OF ACC TO LOCATION 7 REG MOV Rr Ýdata Move Immediate Data to Data M...

Page 48: ... 0 0 0 1 1 p1 p0 This is a 2 cycle instruction Data on 8243 port p is moved read to accumulator bits 0 3 Accumulator bits 4 7 are zeroed A0 3 wPp p e 4 7 A4 7 w0 Note Bits 0 1 of the opcode are used to represent PORTS 4 7 If you are coding in binary rather than assembly language the mapping is as follows Bits Port p1 p0 0 0 4 0 1 5 1 0 6 1 1 7 Example INPPT5 MOVD A P5 MOVE PORT 5 DATA TO ACC BITS ...

Page 49: ...e moved to the accumulator The program counter is restored following this operation A w A within page 3 Example Look up ASCII equivalent of hexadecimal code in table contained at the beginning of page 3 Note that ASCII characters are designated by a 7 bit code the eighth bit is always reset TABSCH MOV A ÝOB8H MOVE B8 HEX TO ACC 10111000 ANL A Ý7FH LOGICAL AND ACC TO MASK BIT 7 00111000 MOVP3 A A M...

Page 50: ...Immediate Mask Opcode 1 0 0 0 1 0 p1 p0 d7 d6 d5 d4 d3 d2 d1 d0 This is a 2 cycle instruction Data on port p is logically ORed with an immediately specified mask Pp w Pp OR data p e 1 2 see OUTL instruction Example ORP1 ORL P1 ÝOFH OR PORT 1 CONTENTS WITH MASK FF HEX SET PORT 1 TO ALL ONES ORLD Pp A Logical OR Port 4 7 With Accumulator Mask Opcode 1 0 0 0 1 1 p1 p0 This is a 2 cycle instruction Da...

Page 51: ... 0 1 1 This is a 2 cycle instruction The stack pointer PSW bits 0 2 is decremented The program counter is then restored from the stack PSW bits 4 7 are not restored SP w SP b 1 PC w SP RETR Return With PSW Restore Opcode 1 0 0 1 0 0 1 1 This is a 2 cycle instruction The stack pointer is decremented The program counter and bits 4 7 of the PSW are then restored from the stack Note that RETR should b...

Page 52: ...E BITS 0 6 IS RESTORED CARRY UNCHANGED BIT 7 IS ZERO RR A Rotate Right Without Carry Opcode 0 1 1 1 0 1 1 1 The contents of the accumulator are rotated right one bit Bit 0 is rotated into the bit 7 position A w An a 1 n e 0 6 A7 w A0 Example Assume accumulator contains 10110001 RRNC RRA NEW ACC CONTENTS ARE 11011000 RRC A Rotate Right Through Carry Opcode 0 1 1 0 0 1 1 1 The contents of the accumu...

Page 53: ... recommended setting for interrupt service routines since locations 0 7 are left intact The setting of PSW bit 4 in effect at the time of an interrupt is restored by the RETR instruction when the interrupt service routine is completed Example Assume an IBF interrupt has occurred control has passed to program memory location 3 and PSW bit 4 was zero before the interrupt LOC3 JMP INIT JUMP TO ROUTIN...

Page 54: ...CNT STOP TIMER JMP 7H JUMP TO LOCATION 7 TIMER INTERRUPT ROUTINE STRT CNT Start Event Counter Opcode 0 1 0 0 0 1 0 1 The TEST 1 T1 pin is enabled as the event counter input and the counter is started The event counter register is incremented with each high to low transition on the T1 pin Example Initialize and start event counter Assume overflow is desired with first T1 input STARTC EN TCNTI ENABL...

Page 55: ...ts of the accumulator and the contents of working register r are exchanged A Ý Rr r e 0 7 Example Move PSW contents to Reg 7 without losing accumulator contents XCHAR7 XCH A R7 EXCHANGE CONTENTS OF REG 7 AND ACC MOV A PSW MOVE PSW CONTENTS TO ACC XCH A R7 EXCHANGE CONTENTS OF REG 7 AND ACC AGAIN XCH A Rr Exchange Accumulator and Data Memory Contents Opcode 0 0 1 0 0 0 0 r The contents of the accum...

Page 56: ...ulator With Register Mask Opcode 1 1 0 1 1 r2 r1 r0 Data in the accumulator is EXCLUSIVE ORed with the mask contained in working register r A Ý A XOR Rr r e 0 7 Example XORREG XRL A R5 XOR ACC CONTENTS WITH MASK IN REG 5 XRL A Rr Logical XOR Accumulator With Memory Mask Opcode 1 1 0 1 0 0 0 r Data in the accumulator is EXCLUSIVE ORed with the mask contained in the data memory location address by r...

Page 57: ...gle step feature simplifies program debugging by allowing the user to easily follow program execution Figure 4 1 illustrates a recommended circuit for single step operation while Figure 4 2 shows the timing rela tionship between the SYNC output and the SS input During single step operation PORT 1 and part of PORT 2 are used to output address information In order to retain the normal I O functions ...

Page 58: ... from stop is indicated by the proc essor bringing SYNC low 5 To stop the processor at the next instruction SS must be brought low again before the next SYNC pulseÐ the circuit in Figure 4 1 uses the trailing edge of the previous pulse If SS is left high the processor re mains in the RUN mode Figure 4 1 shows a schematic for implementing single step A single D type flip flop with preset and clear ...

Page 59: ...wer standby operation Power is removed from all system elements except the inter nal data RAM in the low power mode Thus the con tents of RAM can be maintained and the device draws only 10 to 15 of its normal power The VCC pin serves as the 5V power supply pin for all of the UPI 41AH 42AH version s circuitry except the data RAM array The VDD pin supplies only the RAM array In normal operation both...

Page 60: ...puter as a standard peripheral de vice Table 5 1 shows the conditions for data transfer Table 5 1 Data Transfer Controls CS A0 RD WR Condition 0 0 0 1 Read DBBOUT 0 1 0 1 Read STATUS 0 0 1 0 Write DBBIN data set F1 e 0 0 1 1 0 Write DBBIN command set F1 e 1 1 x x x Disable DBB Reading the DBBOUT Register The sequence for reading the DBBOUT register is shown in Figure 5 2 This operation causes the ...

Page 61: ...e interface to each of these proces sors follows 231318 36 Figure 5 5 Writing Commands to DBBIN DESIGN EXAMPLES 8085AH Interface Figure 5 6 illustrates an 8085AH system using a UPI 41A 41AH 42 42AH The 8085AH system uses a multiplexed address and data bus During I O the 8 upper address lines A8 A15 contain the same I O address as the lower 8 address data lines A0 A7 therefore I O address decoding ...

Page 62: ...UPI 41A 41AH 42 42AH USER S MANUAL 231318 37 Figure 5 6 8085AH UPI System 231318 38 Figure 5 7 8088 UPI Minimum Mode System 58 ...

Page 63: ...to an 8080A system In this example a crystal and capacitor are used for UPI 41A 41AH 42 42AH timing reference and pow er on RESET If the 2 MHz 8080A 2 phase clock were used instead of the crystal the UPI 41A 41AH 42 42AH would run at only 16 full speed The A0 and CS inputs are direct connections to the 8080 address bus In larger systems however either of these inputs may be decoded from the 16 add...

Page 64: ...er an IBF or an OBF interrupt 2 If the UPI DBBIN register is empty IBF flag e 0 Master writes a word to the DBBIN register WR CS A0 e 0 0 1 or 0 0 0 If A0 e 1 write command word set F1 If A0 e 0 write data word F1 e 0 3 If the UPI DBBOUT register is full OBF flag e 1 Master reads a word from the DBBOUT register RD CS A0 e 0 0 0 4 UPI recognizes IBF via IBF interrupt or JNIBF Input data or command ...

Page 65: ...UPI 41A 41AH 42 42AH USER S MANUAL 231318 42 Figure 5 11 Distributed Processor System 61 ...

Page 66: ...and expander PORTs 4 7 can be directly addressed with single 2 byte instruc tions Also accumulator bits can be tested in a single operation Scan time for 128 keys is about 10 ms Each matrix point has a unique binary code which is used to address ROM when a key closure is detected Page 3 of ROM contains a look up table with useable codes i e ASCII EBCDIC etc which correspond to each key When a vali...

Page 67: ...ee state inter face port and asynchronous data buffer registers allow it to connect directly to this type of system for efficient two way data transfer The UPI s two on board I O ports provide up to 16 input and output signals to control the printer mecha nism The timer event counter is used for generating a timing sequence to control print head position line feed carriage return and other sequenc...

Page 68: ...ding head The UPI also monitors 4 status lines from the tape transport includ ing end of tape cassette inserted busy and write per mit All control signals can be handled by the UPI s two I O ports Universal I O Interface Figure 6 4 shows an I O interface design based on the UPI This configuration includes 12 parallel I O lines and a serial RS232C interface for full duplex data transfer up to 1200 ...

Page 69: ...l control After a start bit is de tected the interval timer can be preset to generate an interrupt at the proper time for sampling the serial bit stream This eliminates the need for software timing loops and allows the processor to proceed to other tasks i e parallel I O operations between serial bit sam ples Software flags are used so the main program can determine when the interrupt driven recei...

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