UPI-41A/41AH/42/42AH USER’S MANUAL
Location 3 in program memory should contain an un-
conditional jump to the beginning of the IBF interrupt
service routine elsewhere in program memory. At the
end of the service routine, an RETR (Return and Re-
store Status) instruction is used to return control to the
main program. This instruction will restore the pro-
gram counter and PSW bits 4 – 7, providing automatic
restoration of the previously active register bank as
well. RETR also re-enables interrupts.
A timer-overflow interrupt is enabled by the EN
TCNTI instruction and disabled by the DIS TCNTI
instruction. If enabled, this interrupt occurs when the
timer/counter register overflows. A CALL to location
7 is forced and the interrupt routine proceeds as de-
scribed above.
The interrupt service latency is the sum of current in-
struction time, interrupt recognition time, and the in-
ternal call to the interrupt vector address. The worst
case latency time for servicing an interrupt is 7 clock
cycles. Best case latency is 4 clock cycles.
Interrupt Timing
Interrupt inputs may be enabled or disabled under pro-
gram control using EN I, DIS I, EN TCNTI and DIS
TCNTI instructions. Also, a RESET input will disable
interrupts. An interrupt request must be removed be-
fore the RETR instruction is executed to return from
the service routine, otherwise the processor will re-en-
ter the service routine immediately. Thus, the WR and
CS inputs should not be held low longer than the dura-
tion of the interrupt service routine.
The interrupt system is single level. Once an interrupt
is detected, all further interrupt requests are latched but
are not acted upon until execution of an RETR instruc-
tion re-enables the interrupt input logic. This occurs at
the beginning of the second cycle of the RETR instruc-
tion. If an IBF interrupt and a timer-overflow interrupt
occur simultaneously, the IBF interrupt will be recog-
nized first and the timer-overflow interrupt will remain
pending until the end of the interrupt service routine.
External Interrupts
An external interrupt can be created using the UPI-
41A/41AH/42/42AH timer/counter in the event
counter mode. The counter is first preset to FFH and
the EN TCNTI instruction is executed. A timer-over-
flow interrupt is generated by the first high to low tran-
sition of the TEST 1 input pin. Also, if an IBF interrupt
occurs during servicing of the timer/counter interrupt,
it will remain pending until the end of the service rou-
tine.
Host Interrupts And DMA
If needed, two external interrupts to the host system
can be created using the EN FLAGS instruction. This
instruction allocates two I/O lines on PORT 2 (P
24
and
P
25
). P
24
is the Output Buffer Full interrupt request
line to the host system; P
25
is the Input Buffer empty
interrupt request line. These interrupt outputs reflect
the internal status of the OBF flag and the IBF inverted
flag. Note, these outputs may be inhibited by writing a
‘‘0’’ to these pins. Reenabling interrupts is done by
writing a ‘‘1’’ to these port pins. Interrupts are typically
enabled after power on since the I/O ports are set in a
‘‘1’’ condition. The EN FLAG’s effect is only cancelled
by a device RESET.
DMA handshaking controls are available from two
pins on PORT 2 of the UPI-41A/41AH/42/42AH mi-
crocomputer. These lines (P
26
and P
27
) are enabled by
the EN DMA instruction. P
26
becomes DMA request
(DRQ) and P
27
becomes DMA acknowledge (DACK).
The UPI program initiates a DMA request by writing a
‘‘1’’ to P
26
. The DMA controller transfers the data into
the DBBIN data register using DACK which acts as a
chip select. The EN DMA instruction can only be can-
celled by a chip RESET.
RESET
The RESET input provides a means for internal initiali-
zation of the processor. An automatic initialization
pulse can be generated at power-on by simply connect-
ing a 1
m
fd capacitor between the RESET input and
ground as shown in Figure 2-15. It has an internal
pull-up resistor to charge the capacitor and a Schmitt-
trigger circuit to generate a clean transition. A 2-stage
synchronizer has been added to support reliable opera-
tion up to 12.5 MHz.
If automatic initialization is used, RESET should be
held low for at least 10 milliseconds to allow the power
supply to stabilize. If an external RESET signal is used,
RESET may be held low for a minimum of 8 instruc-
tion cycles. Figure 2-15 illustrates a configuration using
an external TTL gate to generate the RESET input.
This configuration can be used to derive the RESET
signal from the 8224 clock generator in an 8080 system.
19
