UPI-41A/41AH/42/42AH USER’S MANUAL
CHAPTER 5
SYSTEM OPERATION
BUS INTERFACE
The UPI-41A/41AH/42/42AH Microcomputer func-
tions as a peripheral to a master processor by using the
data bus buffer registers to handle data transfers. The
DBB configuration is illustrated in Figure 5-1. The UPI
Microcomputer’s 8 three-state data lines (D
7
– D
0
) con-
nect directly to the master processor’s data bus. Data
transfer to the master is controlled by 4 external inputs
to the UPI:
#
A
0
Address Input signifying command or data
#
CS
Chip Select
#
RD Read strobe
#
WR Write strobe
231318 – 32
Figure 5-1. Data Bus Register Configuration
The master processor addresses the UPI-41A/41AH/
42/42AH Microcomputer as a standard peripheral de-
vice. Table 5-1 shows the conditions for data transfer:
Table 5-1. Data Transfer Controls
CS A
0
RD WR
Condition
0
0
0
1
Read DBBOUT
0
1
0
1
Read STATUS
0
0
1
0
Write DBBIN data, set F
1
e
0
0
1
1
0
Write DBBIN command set
F
1
e
1
1
x
x
x
Disable DBB
Reading the DBBOUT Register
The sequence for reading the DBBOUT register is
shown in Figure 5-2. This operation causes the 8-bit
contents of the DBBOUT register to be placed on the
system Data Bus. The OBF flag is cleared automatical-
ly.
Reading STATUS
The sequence for reading the UPI Microcomputer’s 8
STATUS bits is shown in Figure 5-3. This operation
causes the 8-bit STATUS register contents to be placed
on the system Data Bus as shown.
231318 – 33
Figure 5-2. DBBOUT Read
231318 – 34
BUS CONTENTS DURING STATUS READ
ST
7
ST
6
ST
5
ST
4
F
1
F
0
IBF
OBF
D7
D6
D5
D4
D3
D2
D1
D0
Figure 5-3. Status Read
56
