Register
Description
R
Intel
®
82925X/82925XE MCH Datasheet
41
Figure 3-4. Memory Map to PCI Express* Device Configuration Space
MemMap_PCIExpress
Bus 255
0xFFFFFFFh
Bus 1
Bus 0
0x1FFFFFh
0xFFFFFh
0h
Device 31
0xFFFFFh
Device 1
Device 0
0xFFFFh
0x7FFFh
Function 7
0xFFFFFh
Function 1
Function 0
0xFFFFh
0x7FFFh
0xFFFh
PCI
Compatible
Config Space
PCI
Compatible
Config Header
0xFFh
0x3Fh
PCI Express
Extended
Configuration
Space
Located By PCI
Express Base
Address
Just the same as with PCI devices, each device is selected based on decoded address information
that is provided as a part of the address portion of Configuration Request packets. A PCI Express
device will decode all address information fields (bus, device, function, and extended address
numbers) to provide access to the correct register.
To access this space (steps 1, 2, 3 are performed only once by BIOS)
1.
Use the PCI compatible configuration mechanism to enable the PCI Express enhanced
configuration mechanism by writing 1 to bit 31 of the DEVEN register.
2.
Use the PCI compatible configuration mechanism to write an appropriate PCI Express base
address into the PCIEXBAR register.
3.
Calculate the host address of the register you wish to set using (PCI Express base + (bus
number * 1 MB) + (device number * 32 KB) + (function number * 4 KB) + (1 B * offset
within the function) = host address).
4.
Use a memory write or memory read cycle to the calculated host address to write to or read
from that register.
Base
31
28
20 19
15 14
11
8
2
7
0
1
Config_Write
X
Bus
Device
Function Extended
Register
Number
27
12
X
PCI Express Configuration Writes
Internally the host interface unit translates writes to PCI Express extended configuration space to
configurations on the backbone. Writes to extended space are posted on the FSB, but non-posted
on the PCI Express* x16 Graphics Interface or DMI pins (i.e., translated to configuration writes).
See the
PCI Express Specification
for more information on both the PCI 2.3 compatible and PCI
Express enhanced configuration mechanism and transaction rules.
Summary of Contents for 82925X
Page 78: ...Host Bridge DRAM Controller Registers D0 F0 R 78 Intel 82925X 82925XE MCH Datasheet...
Page 98: ...EPBAR Registers Egress Port Register Summary R 98 Intel 82925X 82925XE MCH Datasheet...
Page 108: ...DMIBAR Registers Direct Media Interface DMI RCRB R 108 Intel 82925X 82925XE MCH Datasheet...
Page 156: ...Host PCI Express Graphics Bridge Registers D1 F0 R 156 Intel 82925X 82925XE MCH Datasheet...
Page 172: ...System Address Map R 172 Intel 82925X 82925XE MCH Datasheet...
Page 192: ...Electrical Characteristics R 192 Intel 82925X 82925XE MCH Datasheet...
