MCHBAR
Registers
R
Intel
®
82925X/82925XE MCH Datasheet
83
5.1.5
C0DRA0—Channel A DRAM Rank 0,1 Attribute
MMIO Range:
MCHBAR
Address Offset:
108h
Default Value:
00h
Access: R/W
Size: 8
bits
The
DRAM Rank Attribute Registers
define the page sizes to be used when accessing different
ranks. These registers should be left with their default value (all zeros) for any rank that is
unpopulated, as determined by the corresponding CxDRB registers. Each byte of information in
the
CxDRA
registers describes the page size of a pair of ranks.
Channel and Rank Map:
Channel A Rank 0, 1:
108h
Channel A Rank 2, 3:
109h
Channel B Rank 0, 1:
188h
Channel B Rank 2, 3:
189h
Bit Access
&
Default
Description
7
Reserved
6:4 R/W
000b
Channel A DRAM odd Rank Attribute:
This 3 bit field defines the page size of
the corresponding rank.
000 = Unpopulated
001 = Reserved
010 = 4 KB
011 = 8 KB
100 = 16 KB
Others = Reserved
3
Reserved
2:0 R/W
000b
Channel A DRAM even Rank Attribute:
This 3 bit field defines the page size of
the corresponding rank.
000 = Unpopulated
001 = Reserved
010 = 4 KB
011 = 8 KB
100 = 16 KB
Others = Reserved
5.1.6
C0DRA2—Channel A DRAM Rank 2,3 Attribute
MMIO Range:
MCHBAR
Address Offset:
109h
Default Value:
00h
Access: R/W
Size: 8
bits
The operation of this register is detailed in the description for register C0DRA0.
Summary of Contents for 82925X
Page 78: ...Host Bridge DRAM Controller Registers D0 F0 R 78 Intel 82925X 82925XE MCH Datasheet...
Page 98: ...EPBAR Registers Egress Port Register Summary R 98 Intel 82925X 82925XE MCH Datasheet...
Page 108: ...DMIBAR Registers Direct Media Interface DMI RCRB R 108 Intel 82925X 82925XE MCH Datasheet...
Page 156: ...Host PCI Express Graphics Bridge Registers D1 F0 R 156 Intel 82925X 82925XE MCH Datasheet...
Page 172: ...System Address Map R 172 Intel 82925X 82925XE MCH Datasheet...
Page 192: ...Electrical Characteristics R 192 Intel 82925X 82925XE MCH Datasheet...