System Address Map
R
Intel
®
82925X/82925XE MCH Datasheet
165
9.3.2 HSEG
(FEDA_0000h–FEDB_FFFFh)
This optional segment from FEDA_0000h to FEDB_FFFFh provides a remapping window to
SMM memory. It is sometimes called the High SMM memory space. SMM-mode processor
accesses to the optionally enabled HSEG are remapped to 000A_0000h – 000B_FFFFh. Non-
SMM-mode processor accesses to enabled HSEG are considered invalid and are terminated
immediately on the FSB. The exceptions to this rule are Non-SMM-mode write-back cycles that
are remapped to SMM space to maintain cache coherency. PCI Express and DMI originated
cycles to enabled SMM space are not allowed. Physical main memory behind the HSEG
transaction address is not remapped and is not accessible. All cacheline writes with WB attribute
or Implicit write backs to the HSEG range are completed to DRAM like an SMM cycle.
9.3.3
FSB Interrupt Memory Space (FEE0_0000h–FEEF_FFFFh)
The FSB Interrupt space is the address used to deliver interrupts to the FSB. Any device on PCI
Express or DMI may issue a memory write to 0FEEx_xxxxh. The MCH will forward this memory
write along with the data to the FSB as an Interrupt Message Transaction. The MCH terminates
the FSB transaction by providing the response and asserting HTRDY#. This memory write cycle
does not go to main memory.
9.3.4
High BIOS Area
The top 2 MB (FFE0_0000h – FFFF_FFFFh) of the PCI memory address range is reserved for
system BIOS (High BIOS), extended BIOS for PCI devices, and the A20 alias of the system
BIOS. The processor begins execution from the High BIOS after reset. This region is mapped to
the DMI so that the upper subset of this region aliases to the 16-MB–256-KB range
.
The actual
address space required for the BIOS is less than 2 MB, but the minimum processor MTRR range
for this region is 2 MB; thus, that full 2 MB must be considered.
9.3.5
PCI Express* Configuration Address Space
A configuration register defines the base address for the 256-MB block of addresses below top of
addressable memory (4 GB) for the configuration space associated with all devices and functions
that are potentially a part of the PCI Express root complex hierarchy. This range will be aligned to
a 256-MB boundary. BIOS must assign this address range such that it will not conflict with any
other address ranges.
Summary of Contents for 82925X
Page 78: ...Host Bridge DRAM Controller Registers D0 F0 R 78 Intel 82925X 82925XE MCH Datasheet...
Page 98: ...EPBAR Registers Egress Port Register Summary R 98 Intel 82925X 82925XE MCH Datasheet...
Page 108: ...DMIBAR Registers Direct Media Interface DMI RCRB R 108 Intel 82925X 82925XE MCH Datasheet...
Page 156: ...Host PCI Express Graphics Bridge Registers D1 F0 R 156 Intel 82925X 82925XE MCH Datasheet...
Page 172: ...System Address Map R 172 Intel 82925X 82925XE MCH Datasheet...
Page 192: ...Electrical Characteristics R 192 Intel 82925X 82925XE MCH Datasheet...
