Functional Description
R
176
Intel
®
82925X/82925XE MCH Datasheet
10.3
System Memory Configuration Register Overview
The configuration registers located in the PCI configuration space of the MCH control the system
memory operation. Following is a brief description of configuration registers.
•
DRAM Rank Boundary (CxDRBy):
The x represents a channel, either A (where x = 0) or
B (where x = 1). The y represents a rank, 0 through 3. DRB registers define the upper
addresses for a rank of DRAM devices in a channel. When the MCH is configured in
asymmetric mode, each register represents a single rank. When the MCH is configured in a
dual interleaved mode, each register represents a pair of corresponding ranks in opposing
channels. There are 4 DRB registers for each channel.
•
DRAM Rank Architecture (CxDRAy):
The x represents a channel, either A (where x = 0)
or B (where x = 1). The y represents a rank, 0 through 3. DRA registers specify the
architecture features of each rank of devices in a channel. The only architecture feature
specified is page size. When the MCH is configured in asymmetric mode, each DRA
represents a single rank in a single channel. When the MCH is configured in a dual-channel
lock-step or interleaved mode, each DRA represents a pair of corresponding ranks in
opposing channels. There are 4 DRA registers per channel. Each requires only 3 bits, so there
are two DRAs packed into a byte.
•
Clock Configuration (CLKCFG):
Specifies DRAM frequency. The same clock frequency
will be driven to all DIMMs.
•
DRAM Timing (CxDRTy):
The x represents a channel, A (where x = 0) or B
(where x = 1). A second register for a channel is differentiated by y, A or B. The DRT
registers define the timing parameters for all devices in a channel. The BIOS programs this
register with “least common denominator” values after reading the SPD registers of each
DIMM in the channel.
•
DRAM Control (CxDRCy):
The x represents a channel, A (where x = 0) or B
(where x = 1). A second register for a channel is differentiated by y, A or B. DRAM refresh
mode, rate, and other controls are selected here.
Summary of Contents for 82925X
Page 78: ...Host Bridge DRAM Controller Registers D0 F0 R 78 Intel 82925X 82925XE MCH Datasheet...
Page 98: ...EPBAR Registers Egress Port Register Summary R 98 Intel 82925X 82925XE MCH Datasheet...
Page 108: ...DMIBAR Registers Direct Media Interface DMI RCRB R 108 Intel 82925X 82925XE MCH Datasheet...
Page 156: ...Host PCI Express Graphics Bridge Registers D1 F0 R 156 Intel 82925X 82925XE MCH Datasheet...
Page 172: ...System Address Map R 172 Intel 82925X 82925XE MCH Datasheet...
Page 192: ...Electrical Characteristics R 192 Intel 82925X 82925XE MCH Datasheet...
