R
Intel
®
82925X/82925XE MCH Datasheet
7
9.3.3
FSB Interrupt Memory Space (FEE0_0000h–FEEF_FFFFh) ............ 165
9.3.4
High BIOS Area .................................................................................. 165
9.3.5
PCI Express* Configuration Address Space ...................................... 165
9.3.6
PCI Express* Graphics Attach............................................................ 166
9.3.7
AGP DRAM Graphics Aperture .......................................................... 166
9.4
System Management Mode (SMM) ................................................................... 167
9.4.1
SMM Space Definition ........................................................................ 167
9.4.2
SMM Space Restrictions .................................................................... 168
9.4.3
SMM Space Combinations ................................................................. 168
9.4.4
SMM Control Combinations................................................................ 169
9.4.5
SMM Space Decode and Transaction Handling ................................ 169
9.4.6
Processor WB Transaction to an Enabled SMM Address Space ...... 169
9.4.7
SMM Access through GTT TLB.......................................................... 170
9.4.8
Memory Shadowing ............................................................................ 170
9.4.9
I/O Address Space.............................................................................. 170
9.4.10
PCI Express* I/O Address Mapping ................................................... 171
9.4.11
MCH Decode Rules and Cross-Bridge Address Mapping ................. 171
9.4.12
Legacy VGA and I/O Range Decode Rules ....................................... 171
10
Functional Description .................................................................................................... 173
10.1
Host Interface ..................................................................................................... 173
10.1.1
FSB GTL+ Termination....................................................................... 173
10.1.2
FSB Dynamic Bus Inversion ............................................................... 173
10.1.3
APIC Cluster Mode Support ............................................................... 174
10.2
System Memory Controller................................................................................. 174
10.2.1
Memory Organization Modes.............................................................. 174
10.3
System Memory Configuration Register Overview ............................................ 176
10.3.1
DRAM Technologies and Organization .............................................. 177
10.3.1.1
Rules for Populating DIMM Slots ...................................... 177
10.3.1.2
System Memory Supported Configurations ...................... 178
10.3.1.3
Main Memory DRAM Address Translation and Decoding 178
10.3.2
DRAM Clock Generation .................................................................... 181
10.3.3
Suspend to RAM and Resume ........................................................... 181
10.3.4
DDR2 On-Die Termination.................................................................. 181
10.3.5
DDR2 Off-Chip Driver Impedance Calibration.................................... 181
10.4
PCI Express* ...................................................................................................... 182
10.4.1
Transaction Layer ............................................................................... 182
10.4.2
Data Link Layer................................................................................... 182
10.4.3
Physical Layer..................................................................................... 182
10.5
Power Management ........................................................................................... 183
10.6
Clocking.............................................................................................................. 183
11
Electrical Characteristics................................................................................................. 185
11.1
Absolute Maximum Ratings................................................................................ 185
11.2
Power Characteristics ........................................................................................ 186
11.3
Signal Groups..................................................................................................... 187
11.4
General DC Characteristics ............................................................................... 189
12
Ballout and Package Information .................................................................................... 193
12.1
Ballout................................................................................................................. 193
12.2
Package Information .......................................................................................... 219
Summary of Contents for 82925X
Page 78: ...Host Bridge DRAM Controller Registers D0 F0 R 78 Intel 82925X 82925XE MCH Datasheet...
Page 98: ...EPBAR Registers Egress Port Register Summary R 98 Intel 82925X 82925XE MCH Datasheet...
Page 108: ...DMIBAR Registers Direct Media Interface DMI RCRB R 108 Intel 82925X 82925XE MCH Datasheet...
Page 156: ...Host PCI Express Graphics Bridge Registers D1 F0 R 156 Intel 82925X 82925XE MCH Datasheet...
Page 172: ...System Address Map R 172 Intel 82925X 82925XE MCH Datasheet...
Page 192: ...Electrical Characteristics R 192 Intel 82925X 82925XE MCH Datasheet...