Intel 82925X Datasheet Download Page 117

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Host-PCI Express* Graphics Bridge Registers (D1:F0)

Intel

82925X/82925XE MCH Datasheet

117

8.1.7

CL1—Cache Line Size (D1:F0)

PCI Device:

Address Offset:

0Ch

Default Value:

00h

Access: R/W
Size: 8

bits

Bit Access

Default

Description

7:0 R/W

00h

Cache Line Size (Scratch pad):

This field is implemented by PCI Express*

devices as a read/write field for legacy compatibility purposes but have no impact
on any PCI Express device functionality.

8.1.8

HDR1—Header Type (D1:F0)

PCI Device:

Address Offset:

0Eh

Default Value:

01h

Access: RO
Size: 8

bits

This register identifies the header layout of the configuration space. No physical register exists at
this location.

Bit Access

Default

Description

7:0 RO

01h

Header Type Register (HDR):

This field returns 01h to indicate that this is a

single function device with bridge header layout.

8.1.9

PBUSN1—Primary Bus Number (D1:F0)

PCI Device:

Address Offset:

18h

Default Value:

00h

Access: RO
Size: 8

bits

This register identifies that this “virtual” Host-PCI Express bridge is connected to PCI bus 0.

Bit Access

Default

Description

7:0 RO

00h

Primary Bus Number (BUSN):

Configuration software typically programs this

field with the number of the bus on the primary side of the bridge. Since device 1
is an internal device and its primary bus is always 0, these bits are read only and
are hardwired to 0.

Summary of Contents for 82925X

Page 1: ...R Intel 925X 925XE Express Chipset Datasheet For the Intel 82925X 82925XE Memory Controller Hub MCH November 2004 Document Number 301464 003...

Page 2: ...cations Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Look f...

Page 3: ...ull downs 30 3 Register Description 35 3 1 Register Terminology 35 3 2 Platform Configuration 37 3 3 General Routing Configuration Accesses 38 3 3 1 Standard PCI Bus Configuration Mechanism 38 3 3 2 L...

Page 4: ...RAM System Management RAM Control D0 F0 71 4 1 30 ESMRAMC Extended System Management RAM Control D0 F0 72 4 1 31 ERRSTS Error Status D0 F0 72 4 1 32 ERRCMD Error Command D0 F0 74 4 1 33 SMICMD SMI Com...

Page 5: ...10 DMIVC1RSTS DMI VC1 Resource Status 106 7 1 11 DMILCAP DMI Link Capabilities 106 7 1 12 DMILCTL DMI Link Control 107 7 1 13 DMILSTS DMI Link Status 107 8 Host PCI Express Graphics Bridge Registers D...

Page 6: ...egister 1 D1 F0 147 8 1 47 PVCCAP2 Port VC Capability Register 2 D1 F0 148 8 1 48 PVCCTL Port VC Control D1 F0 148 8 1 49 VC0RCAP VC0 Resource Capability D1 F0 149 8 1 50 VC0RCTL VC0 Resource Control...

Page 7: ...10 1 Host Interface 173 10 1 1 FSB GTL Termination 173 10 1 2 FSB Dynamic Bus Inversion 173 10 1 3 APIC Cluster Mode Support 174 10 2 System Memory Controller 174 10 2 1 Memory Organization Modes 174...

Page 8: ...tel 82925X 82925XE MCH Datasheet 13 Testability 221 13 1 Complimentary Pins 221 13 2 XOR Test Mode Initialization 222 13 3 XOR Chain Definition 222 13 4 XOR Chains 222 13 5 Pads Excluded from XOR Mode...

Page 9: ...igure 3 4 Memory Map to PCI Express Device Configuration Space 41 Figure 3 5 Intel 82925X 82925XE MCH Configuration Cycle Flowchart 42 Figure 6 1 Link Declaration Topology 93 Figure 9 1 System Address...

Page 10: ...able 168 Table 9 6 SMM Control Table 169 Table 10 1 Sample System Memory Organization with Interleaved Channels 175 Table 10 2 Sample System Memory Organization with Asymmetric Channels 175 Table 10 3...

Page 11: ...tasheet 11 Revision History Revision Description Date 001 Initial Release June 2004 002 Added Intel Extended Memory 64 Technology Intel EM64T Support Information August 2004 003 Added 82925XE MCH Prod...

Page 12: ...H6 1 GB s each direction 100 MHz reference clock shared with PCI Express Graphics Attach 32 bit downstream addressing Messaging and Error Handling System Memory One or two 64 bit wide DDR2 SDRAM data...

Page 13: ...written to take advantage of Intel EM64T Further details on the 64 bit extension architecture and programming model can be found in the Intel Extended Memory 64 Technology Software Developer Guide at...

Page 14: ...lk_P Channel B Graphics Card PCI Express x16 Graphics Intel 925X 925XE Express Chipset System Memory Display Intel ICH6 Family USB 2 0 8 ports 480 Mb s 4 SATA Ports 150 MB s IDE SIO Flash BIOS PCI Bus...

Page 15: ...utside the host conveying interrupt information to the receiving agent through the same path that normally carries read and write commands PCI Express Third Generation Input Output PCI Express Graphic...

Page 16: ...ended Mode of the Scalable Bus Protocol The MCH supports one or two channels of DDR2 SDRAM The MCH also supports the new PCI Express based external graphics attach Thus the 925X 925XE Express chipset...

Page 17: ...pports DDR2 memory DIMM frequencies of 400 MHz and 533 MHz The speed used in all channels is the speed of the slowest DIMM in the system I O Voltage of 1 8 V for DDR2 I O Voltage of 1 9 V for DDR2 533...

Page 18: ...ured at both ends of the DMI link i e the ICH6 and MCH Features of the DMI include A chip to chip connection interface to ICH6 2 GB s point to point DMI to ICH6 1 GB s each direction 100 MHz reference...

Page 19: ...Accessing the device configuration space in a flat memory mapped fashion Automatic discovery negotiation and training of link out of reset Supports traditional PCI style traffic asynchronous snooped...

Page 20: ...PCI Express PLL This clock uses the fixed 100 MHz Serial Reference Clock GCLKP GCLKN for reference All of the above mentioned clocks are capable of tolerating Spread Spectrum clocking as defined in th...

Page 21: ...Signaling Environment AC Specifications and are AC coupled The buffers are not 3 3 V tolerant Differential voltage specification D D 2 1 2 V maximum Single ended maximum 1 5 V Single ended minimum 0...

Page 22: ...CSM VCC2 VCCA_EXPPLL VCCA_HPLL VCCA_SMPLL VSS Voltage Reference and Power PCI Express x16 Graphics Port EXP_RXN 15 0 EXP_RXP 15 0 EXP_TXN 15 0 EXP_TXP 15 0 EXP_COMPO EXP_COMPI EXP_SLR SCS_B 3 0 SMA_B...

Page 23: ...sition of HCPURST The minimum setup time for this signal is 4 HCLKs The minimum hold time is 2 clocks and the maximum hold time is 20 HCLKs HBREQ0 should be tri stated after the hold time requirement...

Page 24: ...HDSTBN3 HD 63 48 HDINV3 HDSTBP2 HDSTBN2 HD 47 32 HDINV2 HDSTBP1 HDSTBN1 HD 31 16 HDINV1 HDSTBP0 HDSTBN0 HD 15 0 HDINV0 HHIT I O GTL Hit This signal indicates that a caching agent holds an unmodified v...

Page 25: ...ata transfer phase HRS 2 0 O GTL Response Signals These signals indicate the type of response as shown below 000 Response type 001 Idle state 010 Retry response 011 Deferred response 100 Reserved not...

Page 26: ...lumn Address Strobe This signal is used with SRAS_A and SWE_A along with SCS_A to define the SDRAM commands SWE_A O SSTL 1 8 Write Enable This signal is used with SCAS_A and SRAS_A along with SCS_A to...

Page 27: ...Column Address Strobe This signal is used with SRAS_B and SWE_B along with SCS_B to define the SDRAM commands SWE_B O SSTL 1 8 Write Enable This signal is used with SCAS_B and SRAS_B along with SCS_B...

Page 28: ...AC coupled so the only voltage specified is a maximum 1 2 V differential swing Signal Name Type Description EXP_RXN 15 0 EXP_RXP 15 0 I O PCIE PCI Express Graphics Receive Differential Pair EXP_TXN 15...

Page 29: ...ve a Schmitt trigger to avoid spurious resets This signal is required to be 3 3 V tolerant PWROK I HVIN Power OK When asserted PWROK is an indication to the MCH that core power has been stable for at...

Page 30: ...buffers during and immediately after the assertion of RSTIN This table only refers to the contributions on the interface from the MCH and does not reflect any external influence such as external pull...

Page 31: ...HV TRI No VTT HADS I O TERM HV TERM HV TRI No VTT HBNR I O TERM HV TERM HV TRI No VTT HBPRI O TERM HV TERM HV TRI No VTT HDBSY I O TERM HV TERM HV TRI No VTT HDEFER O TERM HV TERM HV TRI No VTT HDRDY...

Page 32: ...3 0 I O TRI TRI TRI SDM_A 7 0 O TRI TRI TRI SCB_A 7 0 1 I O TRI TRI TRI SDQS_A 8 0 2 I O TRI TRI TRI SDQS_A 8 0 2 I O TRI TRI TRI SCKE_A 3 0 O LV LV LV System Memory SODT_A 3 0 O LV LV LV Channel B SC...

Page 33: ...on the 82925X MCH only Table 2 3 PCI Express Graphics x16 Port Reset and S3 States Interface Signal Name I O State During RSTIN Assertion State After RSTIN De assertion S3 Pull up Pull down EXP_RXN 15...

Page 34: ...IN HCLKP I IN IN IN GCLKN I IN IN IN GCLKP I IN IN IN DREFCLKN I IN IN IN Clocks DREFCLKP I IN IN IN Table 2 6 Miscellaneous Reset and S3 States Interface Signal Name I O State During RSTIN Assertion...

Page 35: ...hrough 4095 of each device may only be accessed using memory mapped transactions in DWord 32 bit quantities 3 1 Register Terminology The following table shows the register related terminology that is...

Page 36: ...ites software must ensure that the values of reserved bit positions are preserved That is the values of reserved bit positions must first be read merged with the new values for other bit positions and...

Page 37: ...ration perspective appears to be a hierarchical PCI bus behind a PCI to PCI bridge and therefore has a programmable PCI Bus number The PCI Express Graphics Attach appears to system software to be a re...

Page 38: ...cycles to the proper interface Configuration cycles to the Intel ICH6 internal devices and Primary PCI including downstream devices are routed to the Intel ICH6 via DMI Configuration cycles to both t...

Page 39: ...nternal device 3 3 3 Primary PCI and Downstream Configuration Mechanism If the Bus Number in the CONFIG_ADDRESS is non zero and falls outside the range claimed by the Host PCI Express bridge not betwe...

Page 40: ...ress configuration access mechanism To maintain compatibility with PCI configuration addressing mechanisms system software must access the extended configuration space using 32 bit operations 32 bit a...

Page 41: ...to enable the PCI Express enhanced configuration mechanism by writing 1 to bit 31 of the DEVEN register 2 Use the PCI compatible configuration mechanism to write an appropriate PCI Express base addre...

Page 42: ...ess to PCI Express MCH allows cycle to go to DMI resulting in Master Abort Bus Sec Bus Bus Sub Bus in MCH Dev 1 Bus 0 Device 1 Dev 1 Enabled Function 0 Device 0 Function 0 Device 2 Dev 2 Enabled Funct...

Page 43: ...31 R W 0b Configuration Enable CFGE 1 Enable 0 Disable 30 24 Reserved 23 16 R W 00h Bus Number If the Bus Number is programmed to 00h the target of the Configuration Cycle is a PCI Bus 0 agent If this...

Page 44: ...ld is mapped to byte 6 2 0 of the request header format during PCI Express Configuration cycles and A 10 8 during the DMI configuration cycles 7 2 R W 00h Register Number This field selects one regist...

Page 45: ...ter Address Map Summary Address Offset Register Symbol Register Name Default Value Access 00h 01h VID Vendor Identification 8086h RO 02h 03h DID Device Identification 2580h RO 04h 05h PCICMD PCI Comma...

Page 46: ...able Attribute Map 6 00h R W 97h LAC Legacy Access Control 00h R W 98 9Bh Reserved 9Ch TOLUD Top of Low Usable DRAM 08h R W 9Dh SMRAM System Management RAM Control 00h RO R W L 9Eh ESMRAMC Extended Sy...

Page 47: ...ndary Address 0 00h R W 181h C1DRB1 Channel B DRAM Rank Boundary Address 1 00h R W 182h C1DRB2 Channel B DRAM Rank Boundary Address 2 00h R W 183h C1DRB3 Channel B DRAM Rank Boundary Address 3 00h R W...

Page 48: ...ter uniquely identifies any PCI device Bit Access Default Description 15 0 RO 8086h Vendor Identification Number VID PCI standard identification for Intel 4 1 2 DID Device Identification D0 F0 PCI Dev...

Page 49: ...he ERRCMD register The error status is reported in the ERRSTS and PCISTS registers If SERRE is clear then the SERR message is not generated by the MCH for Device 0 0 Disable Note That this bit only co...

Page 50: ...ter Abort completion packet 11 RO 0b Signaled Target Abort Status STAS The MCH will not generate a Target Abort DMI completion packet or Special Cycle This bit is not implemented in the MCH and is har...

Page 51: ...ister 4 1 6 CC Class Code D0 F0 PCI Device 0 Address Offset 09h Default Value 060000h Access RO Size 24 bits This register identifies the basic function of the device a more specific sub class and a r...

Page 52: ...ader layout of the configuration space No physical register exists at this location Bit Access Default Description 7 0 RO 00h PCI Header HDR This field always returns 0 to indicate that the MCH is a s...

Page 53: ...eld should be programmed during BIOS initialization After it has been written once it becomes read only 4 1 11 CAPPTR Capabilities Pointer D0 F0 PCI Device 0 Address Offset 34h Default Value E0h Acces...

Page 54: ...ant memory mapped space On reset this register is disabled and must be enabled by writing a 1 to EPBAREN Dev 0 offset 54h bit 27 Bit Access Default Description 31 12 R W 00000h Egress Port MMIO Base A...

Page 55: ...compliant memory mapped space On reset this register is disabled and must be enabled by writing a 1 to MCHBAREN Dev 0 offset 54h bit 28 Bit Access Default Description 31 14 R W 00000h MCH Memory Mappe...

Page 56: ...s than the maximum address written to the Top of physical memory register TOLUD If a system is populated with more than 3 5 GB either the PCI Express Enhanced Access mechanism must be disabled or the...

Page 57: ...ed The 4 KB that is reserved by this register does not alias to any PCI 2 3 compliant memory mapped space On reset this register is disabled and must be enabled by writing a 1 to the DMIBAREN Dev 0 of...

Page 58: ...es within the MCH These translated cycles are routed as shown in the table above 30 Reserved 29 R W 0b DMIBAR Enable DMIBAREN 0 DMIBAR is disabled and does not claim any memory 1 DMIBAR memory mapped...

Page 59: ...address of main memory for which an error single bit or multi bit error has occurred Note that the value of this bit field represents the address of the first single or the first multiple bit error oc...

Page 60: ...this field with a syndrome that describes the set of bits associated with the first QW containing an error Note that this field is locked from the time that it is loaded up to the time when the error...

Page 61: ...ce Code This field is updated concurrently with DERRSYN 00h Processor to memory reads 01h 07h Reserved 08h 09h DMI VC0 initiated and targeting cycles data 0Ah 0Bh DMI VC1 initiated and targeting cycle...

Page 62: ...claimed by the MCH and directed to main memory Conversely when WE 0 the host write accesses are directed to Primary PCI The RE and WE attributes permit a memory segment to be Read Only Write Only Rea...

Page 63: ...FFh 00 DRAM Disabled Accesses are directed to the DMI 01 Read Only All reads are serviced by DRAM All writes are forwarded to the DMI 10 Write Only All writes are sent to DRAM Reads are serviced by DM...

Page 64: ...1 Read Only All reads are serviced by DRAM All writes are forwarded to the DMI 10 Write Only All writes are sent to DRAM Reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are ser...

Page 65: ...FFh 00 DRAM Disabled Accesses are directed to the DMI 01 Read Only All reads are serviced by DRAM All writes are forwarded to the DMI 10 Write Only All writes are sent to DRAM Reads are serviced by DM...

Page 66: ...FFh 00 DRAM Disabled Accesses are directed to the DMI 01 Read Only All reads are serviced by DRAM All writes are forwarded to the DMI 10 Write Only All writes are sent to DRAM Reads are serviced by DM...

Page 67: ...FFh 00 DRAM Disabled Accesses are directed to the DMI 01 Read Only All reads are serviced by DRAM All writes are forwarded to the DMI 10 Write Only All writes are sent to DRAM Reads are serviced by DM...

Page 68: ...FFh 00 DRAM Disabled Accesses are directed to the DMI 01 Read Only All reads are serviced by DRAM All writes are forwarded to the DMI 10 Write Only All writes are sent to DRAM Reads are serviced by DM...

Page 69: ...et then accesses to I O address range x3BCh x3BFh are forwarded to the DMI If the VGA enable bit is set and MDA is not present then accesses to I O address range x3BCh x3BFh are forwarded to PCI Expre...

Page 70: ...yte above the maximum DRAM memory that is usable by the operating system Address bits 31 down to 27 programmed to 01h implies a minimum memory size of 128 MBs Configuration software must set this valu...

Page 71: ...te that the D_CLS bit only applies to Compatible SMM space 4 R W L 0b SMM Space Locked D_LCK When D_LCK is set to 1 D_OPEN is reset to 0 and D_LCK D_OPEN C_BASE_SEG H_SMRAM_EN TSEG_SZ and TSEG_EN beco...

Page 72: ...space and with the D OPEN bit 0 It is software s responsibility to clear this bit The software must write a 1 to this bit to clear it 5 RO 1b SMRAM Cacheable SM_CACHE This bit is forced to 1 by the MC...

Page 73: ...hat a DRAM Throttling condition occurred 0 Software has cleared this flag since the most recent throttling event 6 2 Reserved 1 R WC S 0b 82925X MCH Multiple bit DRAM ECC Error Flag DMERR If this bit...

Page 74: ...cycle when bit 11 of the ERRSTS is set The SERR must not be enabled at the same time as the SMI for the same thermal sensor event 0 Reporting of this condition via SERR messaging is disabled 10 Reser...

Page 75: ...TS register it can generate an SERR SMI or SCI DMI special cycle when enabled in the ERRCMD SMICMD or SCICMD registers respectively Note that one and only one message type can be enabled Bit Access De...

Page 76: ...e when it detects a multiple bit error reported by the DRAM controller 0 Reporting of this condition via SCI messaging is disabled For systems not supporting ECC this bit must be disabled 82925XE MCH...

Page 77: ...RO 1h CAPID Version This field has the value 0001b to identify the first revision of the CAPID register definition 23 16 RO 09h CAPID Length This field has the value 09h to indicate the structure len...

Page 78: ...Host Bridge DRAM Controller Registers D0 F0 R 78 Intel 82925X 82925XE MCH Datasheet...

Page 79: ...0Dh Reserved 10E 10F C0BNKARC Channel A DRAM Bank Architecture 0000h R W 110 113h Reserved 114 117h C0DRT1 Channel A DRAM Timing Register 900122h R W 118 11Fh Reserved 120 123h C0DRC0 Channel A DRAM C...

Page 80: ...of 32 MB Each rank has its own single byte DRB register These registers are used to determine which chip select will be active for a given address Channel and Rank Map Channel A Rank 0 100h Channel A...

Page 81: ...een populated in the first rank of each channel and the top address in that rank of either channel is 64 MB Programming guide C0DRB0 C1DRB0 Total memory in chA rank0 in 32 MB increments C0DRB1 C1DRB1...

Page 82: ...n for register C0DRB0 5 1 3 C0DRB2 Channel A DRAM Rank Boundary Address 2 MMIO Range MCHBAR Address Offset 102h Default Value 00h Access R W Size 8 bits The operation of this register is detailed in t...

Page 83: ...ank Map Channel A Rank 0 1 108h Channel A Rank 2 3 109h Channel B Rank 0 1 188h Channel B Rank 2 3 189h Bit Access Default Description 7 Reserved 6 4 R W 000b Channel A DRAM odd Rank Attribute This 3...

Page 84: ...i state the corresponding clock pair 1 Enable the corresponding clock pair 3 R W 0b DIMM Clock Gate Enable Pair 3 0 Tri state the corresponding clock pair 1 Enable the corresponding clock pair 2 R W 0...

Page 85: ...his register is used to program the bank architecture for each Rank Bit Access Default Description 15 8 Reserved 7 6 R W 00b Rank 3 Bank Architecture 00 4 Bank 01 8 Bank 1X Reserved 5 4 R W 00b Rank 2...

Page 86: ...nks This bit controls the maximum number of clocks that a DRAM bank can remain open After this time period the DRAM controller will guarantee to pre charge the bank This time period may or may not be...

Page 87: ...te command and a read or write command to that row 000 2 DRAM clocks 001 Reserved 010 4 DRAM clocks 011 5 DRAM clocks 100 111 Reserved 3 Reserved 2 0 R W 010b DRAM RAS Precharge tRP This bit controls...

Page 88: ...ller and the BIOS BIOS sets this bit to 1 after initialization of the DRAM memory array is complete 28 11 Reserved 10 8 R W 000b Refresh Mode Select RMS This field determines whether refresh is enable...

Page 89: ...n this event all CKE signals are asserted During entry to other low power states C3 S1 MCH internal signal triggers DRAM controller to flush pending commands and enter all ranks into Self Refresh mode...

Page 90: ...ion for register C0DRB0 5 1 13 C1DRB2 Channel B DRAM Rank Boundary Address 2 MMIO Range MCHBAR Address Offset 182h Default Value 00h Access R W Size 8 bits The operation of this register is detailed i...

Page 91: ...register C0DCLKDIS 5 1 18 C1BNKARC Channel B Bank Architecture MMIO Range MCHBAR Address Offset 18Eh Default Value 0000h Access R W Size 16 bits The operation of this register is detailed in the descr...

Page 92: ...aced in self refresh as a result of a Power State or a Reset Warn sequence It is cleared by power management hardware before starting Channel B self refresh exit sequence initiated by a power manageme...

Page 93: ...00h R WO RO 050h 053h EPLE1D EP Link Entry 1 Description 0100h R WO RO 058h 05Fh EPLE1A EP Link Entry 1 Address 000000000 0000000h R WO RO 060h 063h EPLE2D EP Link Entry 2 Description 02000002h R WO R...

Page 94: ...onfiguration software that this is the default egress port 23 16 R WO 00h Component ID This field identifies the physical component that contains this Root Complex Element Component IDs start at 1 Thi...

Page 95: ...ent IDs start at 1 This value is a mirror of the value in the Component ID field of all elements in this component The value only needs to be written in one of the mirrored fields and it will be refle...

Page 96: ...tains this element as specified by the target component ID 23 16 R WO 00h Target Component ID This field identifies the physical or logical component that is targeted by this link entry A value of 0 i...

Page 97: ...t Value 0000000000008000h Access RO Size 64 bits This register provides the second part of a Link Entry that declares an internal link to another Root Complex Element Bit Access Default Description 63...

Page 98: ...EPBAR Registers Egress Port Register Summary R 98 Intel 82925X 82925XE MCH Datasheet...

Page 99: ...004 007h DMIPVCCAP1 DMI Port VC Capability Register 1 DMIBAR 008 00Bh DMIPVCCAP2 DMI Port VC Capability Register 2 DMIBAR 00C 00Dh DMIPVCCTL DMI Port VC Control DMIBAR 00E 00Fh Reserved DMIBAR 010 01...

Page 100: ...es this is the Virtual Channel capability item 7 1 2 DMIPVCCAP1 DMI Port VC Capability Register 1 MMIO Range DMIBAR Address Offset 004h Default Value 00000001h Access R WO RO Size 32 bits This registe...

Page 101: ...pability This field indicates that the VC arbitration is fixed in the root complex VC1 is highest priority and VC0 is lowest priority 7 1 4 DMIPVCCTL DMI Port VC Control MMIO Range DMIBAR Address Offs...

Page 102: ...no port arbitration table since the arbitration is fixed 23 Reserved 22 16 RO 00h Maximum Time Slots MTS This VC implements fixed arbitration and therefore this field is not used 15 RO 0b Reject Snoo...

Page 103: ...Virtual Channel Identifier ID Indicates the ID to use for this virtual channel 23 20 Reserved 19 17 R W 0h Port Arbitration Select PAS Indicates which port table is being programmed The root complex t...

Page 104: ...DMIBAR Address Offset 01Ch Default Value 00008001h Access RO Size 32 bits Bit Access Default Description 31 24 RO 00h Port Arbitration Table Offset AT This field indicates the location of the port arb...

Page 105: ...s field indicates the ID to use for this virtual channel 23 20 Reserved 19 17 R W 0h Port Arbitration Select PAS This field indicates which port table is being programmed The only permissible value of...

Page 106: ...set 000Ch bit 0 is written with value 1 and PAS offset 0014h bits19 17 has value of 4h 0 This bit is cleared after the table has been updated 7 1 11 DMILCAP DMI Link Capabilities MMIO Range DMIBAR Add...

Page 107: ...prior to entering L0 6 2 Reserved 1 0 R W 00b Active State Link PM Control APMC Indicates whether DMI should enter L0s 00 Disabled 01 L0s entry enabled 10 Reserved 11 Reserved 7 1 13 DMILSTS DMI Link...

Page 108: ...DMIBAR Registers Direct Media Interface DMI RCRB R 108 Intel 82925X 82925XE MCH Datasheet...

Page 109: ...itly documented as Reserved and Zero all bits marked as reserved are part of the Reserved and Preserved type that have historically been the typical definition for Reserved It is important to note tha...

Page 110: ...eserved 80 83h PM_CAPID1 Power Management Capabilities 19029001h or 1902A001h RO 84 87h PM_CS1 Power Management Control Status 00000000h RO R W S 88 8Bh SS_CAPID Subsystem ID and Vendor ID Capabilitie...

Page 111: ...C Control 0000h R W 10E 10Fh Reserved 110 113h VC0RCAP VC0 Resource Capability 00000000h RO 114 117h VC0RCTL VC0 Resource Control 8000007Fh RO R W 118 119h Reserved 11A 11Bh VC0RSTS VC0 Resource Statu...

Page 112: ...es any PCI device Bit Access Default Description 15 0 RO 8086h Vendor Identification VID1 PCI standard identification for Intel 8 1 2 DID1 Device Identification D1 F0 PCI Device 1 Address Offset 02h D...

Page 113: ...bit when set enables reporting of non fatal and fatal errors to the Root Complex Note that errors are reported if enabled either through this bit or through the PCI Express specific bits in the Devic...

Page 114: ...when the data is available 1 R W 0b Memory Access Enable MAE 0 All of device 1 s memory space is disabled 1 Enable the Memory and Pre fetchable memory address ranges defined in the MBASE1 MLIMIT1 PMB...

Page 115: ...nality there is no scenario where this bit will get set Because hardware will never set this bit it is impossible for software to have an opportunity to clear this bit or otherwise test that it is imp...

Page 116: ...E Express Chipset Specification Update for the value of the Revision Identification Register 8 1 6 CC1 Class Code D1 F0 PCI Device 1 Address Offset 09h Default Value 060400h Access RO Size 24 bits Thi...

Page 117: ...the header layout of the configuration space No physical register exists at this location Bit Access Default Description 7 0 RO 01h Header Type Register HDR This field returns 01h to indicate that thi...

Page 118: ...guration software with the bus number assigned to PCI Express G 8 1 11 SUBUSN1 Subordinate Bus Number D1 F0 PCI Device 1 Address Offset 1Ah Default Value 00h Access R W Size 8 bits This register ident...

Page 119: ...IOS must not set this register to 00h otherwise 0CF8h 0CFCh accesses will be forwarded to the PCI Express hierarchy associated with this device 3 0 Reserved 8 1 13 IOLIMIT1 I O Limit Address D1 F0 PCI...

Page 120: ...t RMA 1 Secondary Side for Type 1 Configuration Space Header Device for requests initiated by the Type 1 Header Device itself receives a completion with Unsupported Request Completion Status 12 R WC 0...

Page 121: ...the register are read write and correspond to the upper 12 address bits A 31 20 of the 32 bit address The bottom 4 bits of this register are read only and return zeroes when read The configuration so...

Page 122: ...used to map non pre fetchable PCI Express Graphics address ranges typically where control status memory mapped I O data structures of the graphics controller will reside and PMBASE and PMLIMIT are us...

Page 123: ...e read write and correspond to address bits A 31 20 of the 40 bit address The lower 8 bits of the Upper Base Address register are read write and correspond to address bits A 39 32 of the 40 bit addres...

Page 124: ...to be FFFFFh Thus the top of the defined memory address range will be at the top of a 1 MB aligned memory block Note that prefetchable memory range is supported to allow segregation by the configurat...

Page 125: ...errupt Connection This field is used to communicate interrupt line routing information POST software writes the routing information into this register as it initializes and configures the system The v...

Page 126: ...ack to Back Enable FB2BEN Hardwired to 0 6 R W 0b Secondary Bus Reset SRESET Setting this bit triggers a hot reset on the corresponding PCI Express Port 5 RO 0b Master Abort Mode MAMODE When acting as...

Page 127: ...1 KB block even if the addresses are within the range defined by the IOBASE and IOLIMIT registers Instead of going to PCI Express Graphics these cycles are forwarded to DMI where they can be subtracti...

Page 128: ...dicate that there are no 3 3Vaux auxiliary current requirements 21 RO 0 b Device Specific Initialization DSI Hardwired to 0 to indicate that special initialization of this device is NOT required befor...

Page 129: ...le from any D State 1 PMEB generation enabled from any D State The setting of this bit has no effect on hardware See PM_CAP 15 11 7 2 Reserved 1 0 R W 00b Power State This field indicates the current...

Page 130: ...next item in the capabilities list which is the PCI Power Management capability 7 0 RO 0D h Capability ID A value of 0Dh identifies this linked list item capability structure as being for SSID SSVID r...

Page 131: ...o a predefined memory address The reporting of the existence of this capability can be disabled by setting MSICH CAPL 0 7Fh In that case walking this linked list will skip this capability and instead...

Page 132: ...cate that the function does not implement the upper 32 bits of the Message Address register and is incapable of generating a 64 bit memory address 6 4 R W 000b Multiple Message Enable MME System softw...

Page 133: ...address 1 0 RO 00b Force DWord Align Hardwired to 0 so that addresses assigned by system software are always aligned on a DWord address boundary 8 1 30 MD Message Data D1 F0 PCI Device 1 Address Offse...

Page 134: ...field identifies this linked list item capability structure as being for PCI Express registers 8 1 32 PEG_CAP PCI Express G Capabilities D1 F0 PCI Device 1 Address Offset A2h Default Value 0141h Acces...

Page 135: ...cess RO Size 32 bits This register indicates PCI Express link capabilities Bit Access Default Description 31 6 Reserved 5 RO 0b Extended Tag Field Supported Hardwired to indicate support for 5 bit Tag...

Page 136: ...generate TLPs exceeding the set value Note All other encodings are reserved 4 Reserved 3 R W 0b Unsupported Request Reporting Enable 0 Disable 1 Enable Unsupported Requests will be reported Note that...

Page 137: ...eceived an Unsupported Request Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control Register 2 R WC 0b Fatal Error Detected 1 Fatal error s...

Page 138: ...lue from ever existing 14 12 R WO 010b L0s Exit Latency This field indicates the length of time this Port requires to complete the transition from L0s to L0 The value 010 b indicates the range of 128...

Page 139: ...d L1 Exit Latencies 5 R W 0b Retrain Link 0 Normal operation 1 Full Link retraining is initiated by directing the Physical Layer LTSSM from L0 L0s or L1 states to the Recovery state This bit always re...

Page 140: ...hat the platform provides on the connector 11 RO 0b Link Training 1 Link training is in progress Hardware clears this bit once Link training is complete 10 RO 0b Training Error 1 This bit is set by ha...

Page 141: ...n with the Slot Power Limit Scale value this field specifies the upper limit on power supplied by slot Power limit in Watts is calculated by multiplying the value in this field by the value in the Slo...

Page 142: ...Reads to this register return the current state of the Attention Indicator Writes to this register set the Attention Indicator and cause the Port to send the appropriate ATTENTION_INDICATOR_ messages...

Page 143: ...Description 15 7 Reserved 6 RO Xb Presence Detect State This bit indicates the presence of a card in the slot 0 Slot Empty 1 Card Present in slot 5 Reserved 4 R WC 0b Command Completed 1 Hot plug con...

Page 144: ...the PME Status bit of the Root Status Register is set when this bit is set from a cleared state 2 R W 0b System Error on Fatal Error Enable This bit controls the Root Complex s response to fatal error...

Page 145: ...ME is pending when the PME Status bit is set When the PME Status bit is cleared by software the PME is delivered by hardware by setting the PME Status bit again and updating the Requestor ID appropria...

Page 146: ...MCH to support PMEs on the PCI Express x16 Graphics Interface port under legacy OSs 1 R W 0b Hot Plug GPE Enable HPGPE 0 Do not generate GPE Hot Plug message when Hot Plug event is received 1 Enable G...

Page 147: ...rsion of the PCI Express specification 15 0 RO 0002h Extended Capability ID Value of 0002 h identifies this linked list item capability structure as being for PCI Express Virtual Channel registers 8 1...

Page 148: ...f 0 indicates that the table is not present due to fixed VC priority 23 8 Reserved 7 0 RO 01h VC Arbitration Capability This field indicates that the only possible VC arbitration scheme is hardware fi...

Page 149: ...ted with PCI Express Virtual Channel 0 Bit Access Default Description 31 RO 1b VC0 Enable For VC0 this is hardwired to 1 and read only as VC0 can never be disabled 30 27 Reserved 26 24 RO 000b VC0 ID...

Page 150: ...as well as whenever the corresponding Virtual Channel is Disabled or the Link is in the DL_Down state It is cleared when the link successfully exits the FC_INIT2 state Before using a Virtual Channel s...

Page 151: ...Link To disable a Virtual Channel the VC Enable bits for that Virtual Channel must be cleared in both Components on a Link Software must ensure that no traffic is using a Virtual Channel at the time i...

Page 152: ...or that Virtual Channel are cleared in both Components on a Link 0 Reserved 8 1 55 RCLDECH Root Complex Link Declaration Enhanced Capability Header D1 F0 PCI Device 1 Address Offset 140h Default Value...

Page 153: ...itration to this Root Complex Element uses this port number value 23 16 R WO 00h Component ID This field indicates the physical component that contains this Root Complex Element Component IDs start at...

Page 154: ...component that contains this element as specified by the target component ID 23 16 R WO 00h Target Component ID This field indicates the physical or logical component that is targeted by this link ent...

Page 155: ...ue 0000000000000FFFh Access RO Size 64 bits This register provides PCI Express status reporting that is required by the PCI Express specification Bit Access Default Description 63 60 Reserved 59 48 RO...

Page 156: ...Host PCI Express Graphics Bridge Registers D1 F0 R 156 Intel 82925X 82925XE MCH Datasheet...

Page 157: ...CI Express or DMI In the absence of more specific references cycle descriptions referencing PCI should be interpreted as the DMI PCI while cycle descriptions referencing PCI Express are related to the...

Page 158: ...ly peer to peer cycles allowed below the top of memory register TOLUD are DMI to PCI Express VGA range writes Figure 9 1 shows the system memory address map in a simplified form Figure 9 1 System Addr...

Page 159: ...KB 0000_0000h 0009_FFFFh in size and is always mapped to the main memory controlled by the MCH 9 1 2 Legacy Video Area A_0000h B_FFFFh The legacy 128 KB VGA memory range frame buffer 000A_0000h 000B_F...

Page 160: ...ne of these devices the MCH must decode cycles in the MDA range 000B_0000h 000B_7FFFh and forward either PCI Express or the DMI In addition to the memory range B0000h to B7FFFh the MCH decodes I O cyc...

Page 161: ...led this segment is not remapped Non snooped accesses from PCI Express or DMI to this region are always sent to main memory Table 9 3 System BIOS Area Memory Segments Memory Segments Attributes Commen...

Page 162: ...will be physical memory that exists yet non addressable therefore this memory is unusable by the system The MCH does not limit main memory address space in hardware Figure 9 3 Main Memory Address Ran...

Page 163: ...of physical main memory minus the value in the TSEG register which is fixed at 1 MB 2 MB or 8 MB 9 2 3 Pre allocated Memory Voids of physical addresses that are not accessible as general system memor...

Page 164: ...2 MB TOLUD Optional HSEG FEDA_0000h to FEDB_FFFFh Possible address range Not guaranteed Programmable windows graphics ranges PCI Express Port could be here 9 3 1 APIC Configuration Space FEC0_0000h FE...

Page 165: ...write to 0FEEx_xxxxh The MCH will forward this memory write along with the data to the FSB as an Interrupt Message Transaction The MCH terminates the FSB transaction by providing the response and ass...

Page 166: ...ess Prefetchable_Memory_Base_Address Address Prefetchable_Memory_Limit_Address It is essential to support a separate Prefetchable range to apply USWC attribute from the processor point of view to that...

Page 167: ...he SMM space 9 4 1 SMM Space Definition SMM space is defined by its addressed SMM space and its DRAM SMM space The addressed SMM space is defined as the range of bus addresses used by the processor to...

Page 168: ...not be reported to the OS as available main memory This is a BIOS responsibility Any address translated through the GMADR TLB must not target main memory from A_0000h F_FFFFh 9 4 3 SMM Space Combinati...

Page 169: ...D_OPEN CPU in SMM Mode SMM Code Access SMM Data Access 0 x X x x Disable Disable 1 0 X 0 0 Disable Disable 1 0 0 0 1 Enable Enable 1 0 0 1 x Enable Enable 1 0 1 0 1 Enable Disable 1 0 1 1 x Invalid In...

Page 170: ...ry range snoop would not be directly to SMM space there would not be a writeback to SMM In fact the writeback would also be invalid because it uses the same translation and goes to address 0h 9 4 8 Me...

Page 171: ...break this into 2 separate transactions This has not been done on previous chipsets I O writes that lie within 8 byte boundaries but cross 4 byte boundaries are assumed to be split into 2 transaction...

Page 172: ...System Address Map R 172 Intel 82925X 82925XE MCH Datasheet...

Page 173: ...als run at 1066 MT s for a maximum bandwidth of 8 5 GB s The FSB interface supports up to 12 simultaneous outstanding transactions The MCH supports only one outstanding deferred transaction on the FSB...

Page 174: ...ance on real applications Addresses are ping ponged between the channels and the switch happens after each cache line 64 byte boundary If two consecutive cache lines are requested both may be retrieve...

Page 175: ...rganization with Interleaved Channels Rank Channel A population Cumulative top address in Channel A Channel B population Cumulative top address in Channel B 3 0 MB 2560 MB 0 MB 2560 MB 2 256 MB 2560 M...

Page 176: ...architecture features of each rank of devices in a channel The only architecture feature specified is page size When the MCH is configured in asymmetric mode each DRA represents a single rank in a sin...

Page 177: ...nel 2 channel 1b row column 1G 1024M 1B 8b 8 GB Though it is possible to put 8 GB in system by stuffing both channels this way the MCH is still limited to 4 GB of addressable space due to the number o...

Page 178: ...2M X 8 13 10 2 8K 256 MB 512 Mbit 32M X 16 13 10 2 8K 256 MB 512 Mbit 64M X 8 13 11 2 16K 512 MB 512 Mbit 64M X 8 14 10 2 8K 512 MB 1 Gbit 64M X 16 14 10 2 8K 512 MB 1 Gbit 128M X 8 14 11 2 16K 1 GB 1...

Page 179: ...r12 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 b0 b1 c11 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 512 Mb x16 4i 8 KB 256 MB r12 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r11 b1 b0 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 512 Mb x8 4i 8 KB...

Page 180: ...6 r5 r4 r3 r2 r1 r0 b0 b1 c11 c9 c8 c7 c6 c5 c4 c3 h c2 c1 c0 512 Mb x16 4i 4 KB 256 MB r12 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r11 b1 b0 c9 c8 c7 c6 c5 c4 c3 h c2 c1 c0 512 Mb x8 4i 8 KB 512 MB r13 r12...

Page 181: ...ove signal integrity of the memory channel by allowing the termination resistance for the DQ DM DQS and DQS signals to be located inside the DRAM devices themselves instead of on the motherboard The M...

Page 182: ...Transaction Layer The upper layer of the PCI Express architecture is the Transaction Layer The Transaction Layer s primary responsibility is the assembly and disassembly of Transaction Layer Packets T...

Page 183: ...ady L3 PM_THRMTRIP output Conditional memory Self Refresh during C2 C3 and C4 states 10 6 Clocking The MCH has PLLs to provide the internal clocks Host PLL This PLL generates the main core clocks in t...

Page 184: ...CIExpressDif f Pair SATADiffPair 25MHz DiffPair PCI Slot Port80PCI GlueChip PCI Slot PCI Slot PCI 33MHz PCI 33MHz PCI 33MHz PCI 33MHz PCI 33MHz PCI 33MHz PCI 33MHz PCI 33MHz Memory Slot 0 Slot 1 Slot...

Page 185: ...x Unit Notes Tstorage Storage Temperature 55 150 C 1 MCH Core VCC 1 5 V Core Supply Voltage with respect to VSS 0 3 1 65 V Host Interface 800 MHz VTT 1 2 V System Bus Input Voltage with respect to VSS...

Page 186: ...y for max current coming through the chipset s supply balls 2 Rail includes PLL current 3 Includes Worst case Leakage 4 Calculated for highest frequencies Table 11 3 DDR2 Power Characteristics Symbol...

Page 187: ...og Analog signal interface Ref Voltage reference signal HVCMOS 2 5 V tolerant high voltage CMOS buffers SSTL 1 8 1 8 V tolerant stub series termination logic Table 11 4 Signal Groups Signal Group Sign...

Page 188: ...SCLK_A 5 0 SCLK_B 5 0 SCLK_B 5 0 1 m DDR2 Reference Voltage SMVREF 1 0 DDR2 Clocks Reset and Miscellaneous Signal Groups n HVCMOS Input EXTTS n1 Miscellaneous Inputs RSTIN PWROK 0 Low Voltage Diff Clo...

Page 189: ...VCCA_HPLL VCCA_EXPPLL z Various PLL s Analog Supply Voltages 1 425 1 5 1 575 V Reference Voltages HVREF d Host Address Data and Common Clock Signal Reference Voltage 2 3 x VTT 2 2 3 x VTT 2 3 x VTT 2...

Page 190: ...DDR2 Output High Voltage 1 5 V 1 ILeak DDR2 k Input Leakage Current 10 A CI O DDR2 k l DDR2 Input Output Pin Capacitance 3 0 6 0 pF 1 5 V PCI Express Interface Specification 1 0a VTX DIFF P P f Diffe...

Page 191: ...0 pF VIL n1 Input Low Voltage 0 8 V VIH n1 Input High Voltage 2 0 V ILEAK n1 Crossing Voltage 100 A 0 Vin VCC3_3 CIN n1 Input Capacitance 4 690 5 370 pF NOTES 1 Determined with 2x MCH DDR2 Buffer Stre...

Page 192: ...Electrical Characteristics R 192 Intel 82925X 82925XE MCH Datasheet...

Page 193: ...llout Figure 12 1 and Figure 12 2 show the 82925X 82925XE MCH ballout as viewed from the top side of the package Table 12 1 provides the MCH ballout sorted by signal name and Table 12 2 provides the M...

Page 194: ...DMI_TXP3 VSS DMI_RXP2 DMI_RXN2 VSS DMI_RXP3 VSS NC VCC VCC VCC VSS VCC VSS W VCC_EXP VCC_EXP VCC_EXP VCC_EXP DMI_TXN3 VCC_EXP VCC_EXP VCC_EXP VCC_EXP EXP_COMPI VSS NC VCC VCC VSS VCC VSS VCC Y VCC_EX...

Page 195: ...S_B7 VSS SDQ_B57 VSS SDM_B7 VSS SDQ_A61 SDQ_A51 SDQ_A60 Y VCC VCC VCC VSS VCC VCC VSS SDQ_B60 VSS SDQS_B7 VSS SCB_A6 VSS VSS SDQ_A50 VSS SDQ_A55 AA VSS VCC VCC VCC VCC VCC VSS VSS VSS SDQ_B56 SDQ_B61...

Page 196: ...7 EXP_RXP0 E11 EXP_RXP1 J11 EXP_RXP10 L6 EXP_RXP11 P10 EXP_RXP12 M8 EXP_RXP13 N6 EXP_RXP14 P7 EXP_RXP15 R6 EXP_RXP2 F9 EXP_RXP3 F7 EXP_RXP4 B3 EXP_RXP5 D5 EXP_RXP6 G6 EXP_RXP7 H8 EXP_RXP8 J6 EXP_RXP9...

Page 197: ...D24 E27 HD25 E25 HD26 G25 HD27 J25 HD28 K25 HD29 L25 HD30 L23 HD31 K23 HD32 J22 HD33 J24 HD34 K22 HD35 J21 HD36 M21 HD37 H23 HD38 M19 HD39 K21 HD40 H20 HD41 H19 HD42 M18 HD43 K18 HD44 K17 HD45 G18 HD4...

Page 198: ...C G12 NC H12 NC H15 NC H17 NC J12 NC K12 NC L12 NC L19 NC N12 NC N22 NC N23 NC N24 NC P12 NC P23 NC P24 NC P30 NC R12 NC R24 NC T12 NC U12 NC V12 NC W12 NC Y12 NC A2 PWROK AG7 RSTIN AF7 RSV H14 RSV J1...

Page 199: ...3 AN8 SCLK_A0 AL29 SCLK_A0 AM30 SCLK_A1 AN2 SCLK_A1 AN3 SCLK_A2 AC34 SCLK_A2 AC35 SCLK_A3 AL28 SCLK_A3 AK28 SCLK_A4 AM3 SCLK_A4 AM2 SCLK_A5 AC33 SCLK_A5 AB34 SCLK_B0 AH23 SCLK_B0 AG23 SCLK_B1 AK9 SCLK...

Page 200: ...SDQ_B07 AH7 SDQ_B08 AK10 SDQ_B09 AL4 SDQ_B10 AL8 SDQ_B11 AF12 SDQ_B12 AH4 SDQ_B13 AJ5 SDQ_B14 AL6 SDQ_B15 AN6 SDQ_B16 AF13 SDQ_B17 AD14 SDQ_B18 AF14 SDQ_B19 AE14 SDQ_B20 AD12 SDQ_B21 AE13 SDQ_B22 AK1...

Page 201: ...Ball SMA_A9 AP22 SMA_A10 AP26 SMA_A11 AP21 SMA_A12 AN20 SMA_A13 AN30 SMA_B0 AN15 SMA_B1 AR15 SMA_B2 AN14 SMA_B3 AP14 SMA_B4 AN13 SMA_B5 AN11 SMA_B6 AP13 SMA_B7 AR11 SMA_B8 AR12 SMA_B9 AP11 SMA_B10 AP...

Page 202: ...1 VCC Y23 VCC Y24 VCC AC1 VCC AC10 VCC AC11 VCC AC2 VCC AC3 VCC AC4 VCC AC5 VCC AC6 VCC AC7 VCC AC8 VCC AC9 VCC AD1 VCC AD10 VCC AD2 VCC AD3 VCC AD4 VCC AD5 VCC AD6 VCC AD7 VCC AD8 VCC AD9 VCC L10 VCC...

Page 203: ...1 MCH Ballout Sorted By Signal Name Signal Name Ball VSS AC25 VSS AC27 VSS AC29 VSS AC31 VSS AC32 VSS AD11 VSS AD13 VSS AD16 VSS AD19 VSS AD20 VSS AD22 VSS AD25 VSS AD26 VSS AD34 VSS AE12 VSS AE21 VSS...

Page 204: ...VSS Y27 VSS Y29 VSS Y31 VSS AF10 VSS AF18 VSS AF21 VSS AF26 VSS AF29 VSS AF31 VSS AF32 VSS AF35 VSS AF4 VSS AF6 VSS AF8 VSS AG12 VSS AG13 VSS AG15 VSS AG16 VSS AG18 VSS AG19 VSS AG21 VSS AG22 VSS AG5...

Page 205: ...S R8 VSS R9 VSS T10 VSS T11 VSS T18 VSS T2 VSS Y32 VSS Y34 VSS A10 VSS A18 VSS A26 VSS A3 VSS A30 VSS A33 VSS A5 VSS AA1 VSS AA10 VSS AA11 VSS AA15 VSS AA17 VSS AA19 VSS AA2 VSS AA25 VSS AJ30 VSS AJ32...

Page 206: ...T4 VSS T5 VSS T6 VSS T7 VSS U11 VSS U15 VSS U17 Table 12 1 MCH Ballout Sorted By Signal Name Signal Name Ball VSS U19 VSS U2 VSS U21 VSS U23 VSS U25 VSS U27 VSS U29 VSS U31 VSS U32 VSS U4 VSS U7 VSS U...

Page 207: ...ber Ball Signal Name A33 VSS A34 NC A35 NC B1 NC B2 VSS B3 EXP_RXP4 B4 EXP_RXN4 B5 VSS B6 VSS B7 VSS B8 VSS B9 VSS B10 VSS B11 GCLKN B12 VSS B13 VCCA_DPLLB B14 VSS B15 RSV B16 VSS B17 VCCA_SMPLL B18 V...

Page 208: ...Signal Name D27 HD60 D28 VSS D29 HD18 D30 VSS D31 VSS D32 VSS D33 HD10 D34 HD8 D35 E1 VSS E2 VSS E3 EXP_TXP6 E4 VSS E5 EXP_RXN5 E6 VSS E7 EXP_RXN3 E8 VSS E9 EXP_RXN2 E10 VSS E11 EXP_RXP0 E12 RSV E13 R...

Page 209: ...ber Ball Signal Name G21 VTT G22 VTT G23 VSS G24 HCPURST G25 HD26 G26 VSS G27 VSS G28 VSS G29 HD20 G30 HA6 G31 HREQ3 G32 HA7 G33 HD7 G34 HD5 G35 HD3 H1 EXP_TXP9 H2 VSS H3 EXP_TXN8 H4 VSS H5 VSS H6 VSS...

Page 210: ...l Number Ball Signal Name K15 RSV K16 EXTTS K17 HD44 K18 HD43 K19 HDINV2 K20 VSS K21 HD39 K22 HD34 K23 HD31 K24 VSS K25 HD28 K26 VSS K27 HA14 K28 VSS K29 HA4 K30 HA8 K31 VSS K32 VSS K33 HA15 K34 HRS0...

Page 211: ...orted By Ball Number Ball Signal Name N9 VSS N10 VSS N11 VSS N12 NC N13 VCC N14 VCC N15 VCC N16 VCC N17 VSS N18 VCC N19 VSS N20 VCC N21 VCC N22 NC N23 NC N24 NC N25 VSS N26 HA19 N27 HADSTB1 N28 VSS N2...

Page 212: ...By Ball Number Ball Signal Name T1 DMI_TXP1 T2 VSS T3 DMI_TXN0 T4 VSS T5 VSS T6 VSS T7 VSS T8 DMI_RXN1 T9 DMI_RXP1 T10 VSS T11 VSS T12 NC T13 VCC T14 VCC T15 VCC T16 VCC T17 VCC T18 VSS T19 VCC T20 V...

Page 213: ...82925X RSV 82925XE V31 SCB_A1 82925X RSV 82925XE V32 SCB_A0 82925X RSV 82925XE V33 SDQ_A57 V34 SDQ_A56 V35 VSS W1 VCC_EXP W2 VCC_EXP W3 VCC_EXP W4 VCC_EXP W5 DMI_TXN3 W6 VCC_EXP W7 VCC_EXP W8 VCC_EXP...

Page 214: ...AA20 VCC AA21 VCC AA22 VCC AA23 VCC AA24 VCC AA25 VSS AA26 VSS AA27 VSS AA28 SDQ_B56 AA29 SDQ_B61 AA30 SCB_A3 82925X RSV 82925XE AA31 SCB_A2 82925X RSV 82925XE AA32 SDQ_A54 AA33 SDM_A6 AA34 SDQS_A6 A...

Page 215: ...VSS AD14 SDQ_B17 AD15 SDQ_B29 AD16 VSS AD17 SDQ_A29 AD18 SDQ_B24 AD19 VSS AD20 VSS AD21 NC AD22 VSS AD23 SDQ_B37 AD24 SDM_B6 AD25 VSS AD26 VSS AD27 SDQ_A35 AD28 SCLK_B5 AD29 SCLK_B5 AD30 NC AD31 SDQ_A...

Page 216: ...P0 AG5 VSS AG6 NC AG7 PWROK AG8 SRCOMP1 AG9 VSS AG10 SDQ_B1 AG11 SDQ_B0 AG12 VSS AG13 VSS AG14 SDQS_B2 AG15 VSS AG16 VSS AG17 SDQS_A3 AG18 VSS AG19 VSS AG20 SDQS_B3 AG21 VSS AG22 VSS AG23 SCLK_B0 AG24...

Page 217: ...J29 SDQ_B44 AJ30 VSS AJ31 SDQ_B41 AJ32 VSS AJ33 SDM_A4 AJ34 SDQ_A45 AJ35 VSS AK1 VSS AK2 SDQ_A8 AK3 SDQ_A9 AK4 VSS AK5 SDM_B1 AK6 VSS AK7 SDQ_A17 AK8 VSS AK9 SCLK_B1 AK10 SDQ_B8 AK11 VSS AK12 SM_SLEWO...

Page 218: ...AM18 NC AM19 VCCSM AM20 VCCSM AM21 NC AM22 VCCSM AM23 VCCSM AM24 NC AM25 VCCSM AM26 VCCSM AM27 VCCSM AM28 VSS AM29 VCCSM AM30 SCLK_A0 AM31 VSS AM32 VCCSM AM33 SCS_B1 AM34 SMA_B13 AM35 AN1 VSS AN2 SCLK...

Page 219: ...AR3 VSS AR4 AR5 SDQ_A20 AR6 VSS AR7 VCCSM AR8 SCKE_B2 AR9 SCKE_B0 AR10 VCCSM AR11 SMA_B7 AR12 SMA_B8 AR13 VSS AR14 VCCSM AR15 SMA_B1 AR16 SBS_B0 AR17 VSS Table 12 2 MCH Ballout Sorted By Ball Number...

Page 220: ...Ballout and Package Information R 220 Intel 82925X 82925XE MCH Datasheet Figure 12 3 MCH Package Dimensions MCH...

Page 221: ...o be driven Table 13 1 Complimentary Pins to Drive Complimentary Pin XOR Chain Complimentary Pin XOR Chain SDQS_A0 SM XOR 6 SDQS_A0 SM XOR 4 SDQS_A1 SM XOR 6 SDQS_A1 SM XOR 4 SDQS_A2 SM XOR 6 SDQS_A2...

Page 222: ...32 clocks Begin testing the XOR chains 13 3 XOR Chain Definition The 82925X 82925XE MCH has 10 XOR chains The XOR chain outputs are driven out on the following output pins During full width testing X...

Page 223: ...HD43 0 7 F17 HD47 0 8 M19 HD38 0 9 K21 HD39 0 10 K19 HDINV2 0 11 H18 HD46 0 12 J19 HDSTBP2 0 13 F19 HDSTBN2 0 14 G18 HD45 0 15 K22 HD34 0 16 M21 HD36 0 17 J21 HD35 0 18 H20 HD40 0 19 H19 HD41 0 20 J2...

Page 224: ...J25 HD27 0 41 K25 HD28 0 42 K23 HD31 0 43 L23 HD30 0 44 J26 HDINV1 0 45 G25 HD26 0 46 L25 HD29 0 47 B32 HD15 0 48 G33 HD7 0 49 H33 HD1 0 50 H35 HD4 0 51 J34 HD2 0 52 G30 HA6 0 53 H29 HA3 0 54 J28 HA13...

Page 225: ...7 C27 HD49 1 8 C28 HD56 1 9 A31 HD53 1 10 C31 HD50 1 11 B31 HD52 1 12 D29 HD18 1 13 E28 HD16 1 14 G29 HD20 1 15 B34 HD11 1 16 B33 HD13 1 17 C32 HD14 1 18 C33 HD9 1 19 C34 HD12 1 20 D34 HD8 1 21 D33 H...

Page 226: ...1 42 L34 HHIT 1 43 M35 HBNR 1 44 L35 HDBSY 1 45 N35 HHITM 1 46 P34 HRS1 1 47 N34 HTRDY 1 48 R33 HBREQ0 1 49 N31 HA21 1 50 N33 HA26 1 51 T31 HA28 1 52 E32 HREQ1 1 53 T27 HA27 1 54 M26 HA20 1 55 N26 HA...

Page 227: ...SDQS_A8 82925X RSV 82925XE 2 12 AA31 SCB_A2 82925X RSV 82925XE 2 13 AA30 SCB_A3 82925X RSV 82925XE 2 14 Y30 SCB_A6 82925X RSV 82925XE 2 15 AB29 SCB_A7 82925X RSV 82925XE 2 16 V31 SCB_A1 82925X RSV 829...

Page 228: ...2 AC33 SCLK_A5 2 33 AF34 SDQ_A47 2 34 AH35 SDQ_A41 2 35 AJ34 SDQ_A45 2 36 AG34 SDM_A5 2 37 AE33 SDQ_A43 2 38 AF33 SDQ_A42 2 39 AG32 SDQ_A46 2 40 AH34 SDQ_A40 2 41 AK34 SDQ_A44 2 42 AG35 SDQS_A5 2 43 A...

Page 229: ...6 3 9 Y26 SDQ_B60 3 10 W27 SDQS_B7 3 11 AB31 SDQS_B6 3 12 AB27 SDQ_B55 3 13 AE31 SDQ_B52 3 14 AC26 SDQ_B50 3 15 AE27 SDQ_B49 3 16 AE29 SDQ_B53 3 17 AF27 SDQ_B48 3 18 AB26 SDQ_B51 3 19 AC28 SDQ_B54 3 2...

Page 230: ...l Name 3 34 AH31 SDM_B5 3 35 AK33 SDQ_B45 3 36 AJ31 SDQ_B41 3 37 AG28 SDQ_B47 3 38 AJ29 SDQ_B44 3 39 AG31 SDQ_B42 3 40 AH28 SDQS_B5 3 41 AM34 SMA_B13 3 42 AJ25 SDQ_B39 3 43 AL25 SDQ_B38 3 44 AJ26 SDQ_...

Page 231: ...8 AK27 SDQS_A4 4 9 AD27 SDQ_A35 4 10 AL30 SDQ_A36 4 11 AJ33 SDM_A4 4 12 AK31 SDQ_A33 4 13 AF28 SDQ_A39 4 14 AH27 SDQ_A34 4 15 AG27 SDQ_A38 4 16 AL31 SDQ_A37 4 17 AK29 SDQ_A32 4 18 AP29 SCAS_A 4 19 AN2...

Page 232: ...nal Name 4 34 AR24 SMA_A3 4 35 AR23 SMA_A6 4 36 AN23 SMA_A8 4 37 AH16 SDQS_A3 4 38 AH17 SDQ_A27 4 39 AL17 SDQ_A26 4 40 AF16 SDQ_A25 4 41 AE17 SDQ_A24 4 42 AD17 SDQ_A29 4 43 AN18 SCKE_A2 4 44 AN7 SDQS_...

Page 233: ...SDQS_B3 5 11 AH19 SDQ_B30 5 12 AD15 SDQ_B29 5 13 AD18 SDQ_B24 5 14 AE20 SDM_B3 5 15 AK19 SDQ_B27 5 16 AH21 SDQ_B31 5 17 AL18 SDQ_B26 5 18 AF15 SDQ_B28 5 19 AE19 SDQ_B25 5 20 AK22 SCLK_B3 5 21 AG23 SC...

Page 234: ...J21 SDQS_B8 82925X RSV 82925XE 5 32 AN17 SRAS_B 5 33 AP18 SCAS_B 5 34 AP17 SWE_B 5 35 AR16 SBS_B0 5 36 AN16 SBS_B1 5 37 AN14 SMA_B2 5 38 AN15 SMA_B0 5 39 AP15 SMA_B10 5 40 AR15 SMA_B1 5 41 AP14 SMA_B3...

Page 235: ...AP22 SMA_A9 6 9 AN22 SMA_A5 6 10 AR20 SBS_A2 6 11 AN21 SMA_A7 6 12 AN20 SMA_A12 6 13 AP19 SCKE_A0 6 14 AR19 SCKE_A3 6 15 AP7 SDQS_A2 6 16 AM9 SDQ_A18 6 17 AL7 SDQ_A19 6 18 AM8 SDQ_A23 6 19 AM7 SDQ_A2...

Page 236: ...mber Signal Name 6 34 AJ3 SDQ_A13 6 35 AJ1 SDQ_A12 6 36 AL1 SDM_A1 6 37 AL3 SDQS_A1 6 38 AG1 SDQS_A0 6 39 AG3 SDQ_A6 6 40 AF2 SDM_A0 6 41 AH2 SDQ_A7 6 42 AH3 SDQ_A2 6 43 AJ2 SDQ_A3 6 44 AF3 SDQ_A1 6 4...

Page 237: ...7 8 AR11 SMA_B7 7 9 AN10 SMA_B12 7 10 AP10 SMA_B11 7 11 AN9 SBS_B2 7 12 AN11 SMA_B5 7 13 AR8 SCKE_B2 7 14 AP9 SCKE_B1 7 15 AN8 SCKE_B3 7 16 AE14 SDQ_B19 7 17 AF14 SDQ_B18 7 18 AK13 SDQ_B22 7 19 AH12...

Page 238: ...Name 7 34 AN6 SDQ_B15 7 35 AL6 SDQ_B14 7 36 AK5 SDM_B1 7 37 AF12 SDQ_B11 7 38 AM5 SDQS_B1 7 39 AH8 SDQS_B0 7 40 AE11 SDQ_B4 7 41 AF11 SDQ_B5 7 42 AG10 SDQ_B1 7 43 AJ7 SDQ_B2 7 44 AJ6 SDQ_B3 7 45 AJ8...

Page 239: ...TXN3 8 9 B4 EXP_RXN4 8 10 C5 EXP_TXN4 8 11 E5 EXP_RXN5 8 12 D2 EXP_TXN5 8 13 G5 EXP_RXN6 8 14 F3 EXP_TXN6 8 15 H7 EXP_RXN7 8 16 G1 EXP_TXN7 8 17 J5 EXP_RXN8 8 18 H3 EXP_TXN8 8 19 K7 EXP_RXN9 8 20 J1 E...

Page 240: ...42 C6 EXP_TXP4 8 43 D5 EXP_RXP5 8 44 C2 EXP_TXP5 8 45 G6 EXP_RXP6 8 46 E3 EXP_TXP6 8 47 H8 EXP_RXP7 8 48 F1 EXP_TXP7 8 49 J6 EXP_RXP8 8 50 G3 EXP_TXP8 8 51 K8 EXP_RXP9 8 52 H1 EXP_TXP9 8 53 L6 EXP_RX...

Page 241: ...Signal Name 9 1 U6 DMI_RXN0 9 2 U5 DMI_RXP0 9 3 T3 DMI_TXN0 9 4 R3 DMI_TXP0 9 5 T8 DMI_RXN1 9 6 T9 DMI_RXP1 9 7 U1 DMI_TXN1 9 8 T1 DMI_TXP1 9 9 V8 DMI_RXN2 9 10 V7 DMI_RXP2 9 11 V3 DMI_TXN2 9 12 U3 DM...

Page 242: ...ll into this category are analog related pins refer to the Table 13 13 Table 13 13 XOR Pad Exclusion List 3GIO FSB SM Miscellaneous GCLKN HCLKN SRCOMP1 DREFCLKN GCLKP HCLKP SRCOMP0 DREFCLKP EXP_COMPO...

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