Intel 82925X, Datasheet

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System Address Map
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166 Intel
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82925X/82925XE MCH Datasheet
9.3.6 PCI Express* Graphics Attach
The MCH can be programmed to direct memory accesses to the PCI Express interface when
addresses are within either of two programmed ranges specified via registers in the MCH’s
Device 1 configuration space.
•
The first range is controlled via the Memory Base Register (MBASE) and Memory Limit
Register (MLIMIT) registers.
•
The second range is controlled via the Prefetchable Memory Base (PMBASE) and
Prefetchable Memory Limit (PMLIMIT) registers.
The MCH positively decodes memory accesses to PCI Express memory address space as defined
by the following equations:
Memory_Base_Address
≤
Address
≤
Memory_Limit_Address
Prefetchable_Memory_Base_Address
≤
Address
≤
Prefetchable_Memory_Limit_Address
It is essential to support a separate Prefetchable range to apply USWC attribute (from the
processor point of view) to that range. The USWC attribute is used by the processor for write
combining.
Note: The programmable ranges are used to allocate memory address space for any PCI Express devices
sitting on PCI Express that require such a window.
The PCICMD1 register can override the routing of memory accesses to PCI Express. In other
words, the memory access enable bit must be set in the device 1 PCICMD1 register to enable the
memory base/limit and prefetchable base/limit windows.
9.3.7 AGP DRAM Graphics Aperture
Unlike AGP4x, PCI Express has no concept of aperture for PCI Express devices. As a result,
there is no need to translate addresses from PCI Express. Therefore, the MCH has no APBASE
and APSIZE registers.