Intel 82925X, Datasheet

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R
4 Intel
®
82925X/82925XE MCH Datasheet
4.1.7 MLT—Master Latency Timer (D0:F0) ................................................... 52
4.1.8 HDR—Header Type (D0:F0) ................................................................ 52
4.1.9 SVID—Subsystem Vendor Identification (D0:F0)................................. 52
4.1.10 SID—Subsystem Identification (D0:F0) ................................................ 53
4.1.11 CAPPTR—Capabilities Pointer (D0:F0) ............................................... 53
4.1.12 EPBAR—Egress Port Base Address (D0:F0) ...................................... 54
4.1.13 MCHBAR—MCH Memory Mapped Register Range Base Address
(D0:F0) .................................................................................................. 55
4.1.14 PCIEXBAR—PCI Express* Register Range Base Address (D0:F0) ... 56
4.1.15 DMIBAR—Root Complex Register Range Base Address (D0:F0) ...... 57
4.1.16 DEVEN—Device Enable (D0:F0) ......................................................... 58
4.1.17 DEAP—DRAM Error Address Pointer (D0:F0) (Intel
®
82925X Only)... 59
4.1.18 DERRSYN—DRAM Error Syndrome (D0:F0) (Intel
®
82925X Only) .... 60
4.1.19 DERRDST—DRAM Error Destination (D0:F0) (Intel
®
82925X Only)... 61
4.1.20 PAM0—Programmable Attribute Map 0 (D0:F0) .................................. 62
4.1.21 PAM1—Programmable Attribute Map 1 (D0:F0) .................................. 63
4.1.22 PAM2—Programmable Attribute Map 2 (D0:F0) .................................. 64
4.1.23 PAM3—Programmable Attribute Map 3 (D0:F0) .................................. 65
4.1.24 PAM4—Programmable Attribute Map 4 (D0:F0) .................................. 66
4.1.25 PAM5—Programmable Attribute Map 5 (D0:F0) .................................. 67
4.1.26 PAM6—Programmable Attribute Map 6 (D0:F0) .................................. 68
4.1.27 LAC—Legacy Access Control (D0:F0) ................................................. 69
4.1.28 TOLUD—Top of Low Usable DRAM (D0:F0) ....................................... 70
4.1.29 SMRAM—System Management RAM Control (D0:F0)........................ 71
4.1.30 ESMRAMC—Extended System Management RAM Control (D0:F0) .. 72
4.1.31 ERRSTS—Error Status (D0:F0) ........................................................... 72
4.1.32 ERRCMD—Error Command (D0:F0) ................................................... 74
4.1.33 SMICMD—SMI Command (D0:F0) ...................................................... 75
4.1.34 SCICMD—SCI Command (D0:F0) ....................................................... 76
4.1.35 SKPD—Scratchpad Data (D0:F0) ........................................................ 76
4.1.36 CAPID0—Capability Identifier (D0:F0) ................................................. 77
5 MCHBAR Registers .......................................................................................................... 79
5.1 MCHBAR Register Details ................................................................................... 80
5.1.1 C0DRB0—Channel A DRAM Rank Boundary Address 0 .................... 80
5.1.2 C0DRB1—Channel A DRAM Rank Boundary Address 1 .................... 82
5.1.3 C0DRB2—Channel A DRAM Rank Boundary Address 2 .................... 82
5.1.4 C0DRB3—Channel A DRAM Rank Boundary Address 3 .................... 82
5.1.5 C0DRA0—Channel A DRAM Rank 0,1 Attribute ................................. 83
5.1.6 C0DRA2—Channel A DRAM Rank 2,3 Attribute ................................. 83
5.1.7 C0DCLKDIS—Channel A DRAM Clock Disable .................................. 84
5.1.8 C0BNKARC—Channel A DRAM Bank Architecture ............................ 85
5.1.9 C0DRT1—Channel A DRAM Timing Register ..................................... 86
5.1.10 C0DRC0—Channel A DRAM Controller Mode 0 ................................. 88
5.1.11 C1DRB0—Channel B DRAM Rank Boundary Address 0 .................... 90
5.1.12 C1DRB1—Channel B DRAM Rank Boundary Address 1 .................... 90
5.1.13 C1DRB2—Channel B DRAM Rank Boundary Address 2 .................... 90
5.1.14 C1DRB3—Channel B DRAM Rank Boundary Address 3 .................... 90
5.1.15 C1DRA0—Channel B DRAM Rank 0,1 Attribute ................................. 90
5.1.16 C1DRA2—Channel B DRAM Rank 2,3 Attribute ................................. 91
5.1.17 C1DCLKDIS—Channel B DRAM Clock Disable .................................. 91
5.1.18 C1BNKARC—Channel B Bank Architecture ........................................ 91
5.1.19 C1DRT1—Channel B DRAM Timing Register 1 .................................. 91