Register
Description
R
Intel
®
82925X/82925XE MCH Datasheet
39
CONFIG_ADDRESS. Any read or write to CONFIG_DATA will result in the MCH translating
the CONFIG_ADDRESS into the appropriate configuration cycle.
The MCH is responsible for translating and routing the processor’s I/O accesses to the
CONFIG_ADDRESS and CONFIG_DATA registers to internal MCH configuration registers,
DMI, or PCI Express.
3.3.2
Logical PCI Bus 0 Configuration Mechanism
The MCH decodes the Bus Number (bits 23:16) and the Device Number fields of the
CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0 the
configuration cycle is targeting a PCI Bus 0 device. The Host-DMI Bridge entity within the MCH
is hardwired as Device 0 on PCI Bus 0. The Host-PCI Express Bridge entity within the MCH is
hardwired as Device 1 on PCI Bus 0. The Intel ICH6 decodes the Type 0 access and generates a
configuration access to the selected internal device.
3.3.3
Primary PCI and Downstream Configuration Mechanism
If the Bus Number in the CONFIG_ADDRESS is non-zero, and falls outside the range claimed
by the Host-PCI Express bridge (not between upper bound in device’s Subordinate Bus Number
register and lower bound in device’s Secondary Bus Number register), the MCH would generate a
Type 1 DMI configuration cycle. This DMI configuration cycle will be sent over the DMI.
If the cycle is forwarded to the Intel ICH6 via the DMI, the Intel ICH6 compares the non-zero
Bus Number with the Secondary Bus Number and Subordinate Bus Number registers of its P2P
bridges to determine if the configuration cycle is meant for ICH6 PCI Express ports one of the
Intel ICH6’s devices, the DMI, or a downstream PCI bus.
Figure 3-2. DMI Type 0 Configuration Address Translation
1
31
30
24 23
16 15
11 10
8 7
2 1
DMI_Typ0_Config
0
Reserved
Bus Number
Device
Number
Function
Double
Word
XX
1
31
30
24 23
16 15
11 10
8 7
2 1
0
Reserved
Bus Number
Device
Number
Function
Double
Word
00
OCFBh
DMI Type 0 Configuration Address Extension
Configuration Address
OCFAh
OCF9h
OCF8h
Summary of Contents for 82925X
Page 78: ...Host Bridge DRAM Controller Registers D0 F0 R 78 Intel 82925X 82925XE MCH Datasheet...
Page 98: ...EPBAR Registers Egress Port Register Summary R 98 Intel 82925X 82925XE MCH Datasheet...
Page 108: ...DMIBAR Registers Direct Media Interface DMI RCRB R 108 Intel 82925X 82925XE MCH Datasheet...
Page 156: ...Host PCI Express Graphics Bridge Registers D1 F0 R 156 Intel 82925X 82925XE MCH Datasheet...
Page 172: ...System Address Map R 172 Intel 82925X 82925XE MCH Datasheet...
Page 192: ...Electrical Characteristics R 192 Intel 82925X 82925XE MCH Datasheet...
