IDT CPS Registers
Revision 1.5
Integrated Device Technology, Inc.
CPS-16/12/8 User Manual
10 - 31
July 10, 2012
10.9 GLOBAL CONFIGURATION REGISTERS
10.9.1 Control Register (CPS_CONTROL)
Table 10.43 Port_0_Mask_Value_1_Block_4 0xE40024
Bit
Field Name
Type
Reset
Value
Comment
31 - 0
MASK_VALUE_1_BLOCK_4
R/W
0x00000000
This value will be used for a bit by bit
comparison against the first 32 bits
received in the packet.
Bit 31 will be a maks for the 129th
comparison bit
Bit 30 will be a mask for the 130th
comparison bit
.
.
.
Bit 0 will be a mask for the 160th
comparison bit
Table 10.44 CPS_CONTROL 0xF2000C
Bit
Field Name
Type
Reset
Value
Comment
0
PORT_RESET_BEHAVIOR
R/W
0b0
Defines action upon reception of an
sRIO reset control symbol
(0 = reset chip, 1 = reset port via
which the symbol was received)
4 - 1
TRACE_OUTPUT_PORT_ENABL
E
R/W
0x0
Defines the output port via which
traced packets are transmitted (only
one valid port at a time.
0x0 Defines Port 0 as the Trace
Port
0x1 Defines Port 1 as the Trace
Port
.
.
.
0xF Defines Port 15 as the Trace
Port
10 - 5
Reserved
11
CUT_THRU_ENABLE
R/W
0b0
0b0: Store and Forward Mode
0b1: Cut Through Mode
12
SYSPLL_HALF_CLK_RATE
R/W
0b0
0 = PLL/1
1 = PLL/2
13
Reserved