IDT CPS Registers
Revision 1.5
Integrated Device Technology, Inc.
CPS-16/12/8 User Manual
10 - 55
July 10, 2012
11
PLL_LANE_2_3_RESET
R/W
0b1
Forces reset of Lanes 0 and 1
0 = Reset
1 = Deassert reset
15 - 12
Reserved
16
LANE23_CTRL_EN
R/W
0b0
Enable separate configuration for Lanes
2 and 3
0 = Lanes 2 and 3 follow the same con-
figuration as for Lanes 0 and 1
1 = Lanes 2 and 3 have a independent
configuration from Lanes 0 and 1
18:17
LAN23_SPEEDSEL
R/W
0b00
Separate Port Speed Selection for
Lanes 2 and 3. Only active if [16] = 1
00 = 1.25 Gbps
01 = 2.5 Gbps
10 = 3.125 Gbps
Default is set by external pins (same as
configuration for Lanes 1 and 2)
21:19
LANE23_TCOEFF
R/W
0b000
Separate Transmitter Pre-emphasis for
Lanes 2 and 3.
Only active if [16] = 1
000 = 0%
001 = 6.5%
010 = 13%
011 = 19.5%
100 = 26%
101 = 32.5%
110 = 39%
111 = 45.5%
22
LANE23_FORCE_REINIT
R/W
0b0
Force init on Lanes 2 and 3.
Only active if [16] = 1
25:23
LANE23_TXDRVSEL
R/W
0b010
Transmitter Drive Strength for Lanes 2
and 3.
Only active if [16] = 1
000 = Maximum
010 = Long Haul
100 = Short Haul
111 = Minimum
31 - 12
Reserved
Table 10.84 QUAD_CTRL_BROADCAST 0xFFF000
Bit
Field Name
Type
Reset
Value
Comment
