IDT I2C Interface
Revision 1.5
Integrated Device Technology, Inc.
CPS-16/12/8 User Manual
4 - 11
July 10, 2012
Figure 4.11 Combined Format: Master Transmits Data to Two Slaves, Both with 10-bit Address
4.4.2
Connecting to Standard-, Fast-, and Hs-Mode Devices as a Slave
The CPS-16/12/8 supports Fast / Standard (F/S) modes of operation. As per the
I
2
C specification
, in mixed
speed communication the CPS-16/12/8 supports HS and Fast-mode devices at 400 kbps, and
Standard-mode devices at 100 kbps. The CPS-16/12/8 supports speed negotiation on mixed speed buses
as defined in the
I
2
C Specification
.
4.4.3
CPS-16/12/8
Memory Access through I
2
C as a Slave
The CPS-16/12/8 supports direct memory access through its I
2
C Interface as defined in the
I
2
C
Specification
. It requires the memory address to be specified during writes to its registers. This provides
directed memory accesses through the I
2
C bus.
The CPS-16/12/8 write procedure requires 22 bits of memory address to be provided following the device
address. Thus, the following are required:
1. A device address (one or two bytes depending on 10-bit/7-bit addressing)
2. A memory address (3 bytes yielding 22-bits of memory address)
3. A 32-bit data payload (4 bytes)
Note that the device address can be configured to any arbitrary value using the external address select
pins. A slave address should also be used that is unique to each device on the bus. IDT also recommends
to avoid using reserved addresses as specified in the
I
2
C Specification
, such as CBUS addresses.
Providing the I
2
C access is correct, the CPS-16/12/8 will respond accordingly – even when the slave
address is set to specification reserved address ranges.
As a slave, the CPS-16/12/8 read procedure has the memory address section of the transfer removed. To
perform a read, the proper access will be to perform a write operation (which provides a 22-bit address) and
then to issue a repeated start after the acknowledge bit following the third byte of memory address. The
master will issue a read command selecting the CPS-16/12/8 through the standard device address
procedure with the R/W bit high. Note that in 10-bit device address mode (ADS is 1), only the two MSBs
need be provided during this read. Data from the previously loaded address will immediately follow the
device address protocol. It will be possible to issue a stop or repeated start anytime during the write data
payload procedure, but it must be before the final acknowledge; that is, canceling the write before the write
operation is completed and performed. Also, the CPS-16/12/8 I
2
C Interface will allow the master to access
other devices attached to the I
2
C bus before returning to select the CPS-16/12/8 for the subsequent read
operation from the loaded address. Subsequent reads will begin at the address specified I
2
C during the last
write.
As a slave, the CPS-16/12/8 supports both indirect and direct memory mapping though the I
2
C Interface.
The indirect memory mapping is implemented using the same standard device address/memory
address/data write and read format as defined above, but the memory address specified is the address for
the indirect memory mapping registers. For direct memory mapping, the same write and read procedures
will be followed except that the memory address specified is the direct memory address.
