IDT About This Manual
Revision 1.5
Integrated Device Technology, Inc.
CPS-16/12/8 User Manual
x
July 10, 2012
vention.
A bit is set when its value is 0b1. A bit is cleared when its value is 0b0.
The compressed notation ABC[x|y|z]D refers to ABCxD, ABCyD, and ABCzD.
The compressed notation ABC[x..y]D refers to ABCxD, ABC(x+1)D, ABC(x+2)D,... ABCyD.
In double words, bit 63 is always the most significant bit and bit 0 is the least significant bit. In
words, bit 31 is always the most significant bit and bit 0 is the least significant bit. In bytes, bit 7 is
always the most significant bit and bit 0 is the least significant bit.
This device follows the Big endian convention. The ordering of bytes within words is referred to as
either “big endian” or “little endian.” Big endian systems label byte zero as the most significant (left-
most) byte of a word. Little endian systems label byte zero as the least significant (rightmost) byte
of a word.
Figure 1
Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition
A read-only: register, bit, or field is one which can be read but not modified
A sticky bit is a bit that remains set after being set by hardware until a zero is written to it. Writing a
one to a sticky has no effect on its value.
A zero field in a register, denoted as “0” in register figures, must be written with a value of zero and
returns a value of zero when read.
Revision History
July 10, 2012
: Revision 1.5. Removed the confidential statements from the document’s footers.
January 19, 2011
: Revision 1.4. Fixed a number of minor errors, updated
, and added
May 21, 2009
: Revision 1.3. Fixed a number of minor errors.
January 19, 2009
: Revision 1.2.
1. Add more detail about the Ack Counter and Nack Counter
2. Add basic device Programming example
3. Add detail explanation about the multicast respond
4. Add explanation about the multicast with responds
5. Add EPROM format example.
June 9, 2008
: Revision 1.1.
Corrected switch chapter text around number of retries allowed for CRC error, as well as multicast
delaying discussion. Fixed /IRQ polarity in Error Handling chapter. Other editorial changes.
September 7, 2007
: Initial release. Revision 1.0.
0
1
2
3
bit 0
bit 31
Address of Bytes within Words: Big Endian
3
2
1
0
bit 0
bit 31
Address of Bytes within Words: Little Endian
