Revision 1.5
Integrated Device Technology, Inc.
CPS-16/12/8 User Manual
4 - 1
July 10, 2012
Chapter 4
I
2
C Interface
4 I
2
C Interface
This chapter discusses the I
2
C capabilities of the CPS-16/12/8.
4.1
Overview
The I
2
C Interface is compliant with the
I
2
C Specification
as a slave device and as a temporary master. The
I
2
C port can be thought of primarily as a control plane access point for the CPS-16/12/8. An external device
such as a host processor can use it to access the CPS-16/12/8’s registers. The port can also be used by
the CPS-16/12/8 to load registers.
The use of the I
2
C port is not targeted as a bridge to other external devices through the CPS-16/12/8’s
RapidIO ports. There is no special safeguard on the I
2
C address assignment inside the device. Users
should assign the I
2
C address as per specification.
4.2
Master/Slave Configuration
The CPS-16/12/8 provides an external signal, MM, to configure the device in Master mode or Slave mode
out of reset. When this signal is tied to V
DD
(1.2V), it configures the device into temporary Master mode
after reset. If left floating, it will configure the device into Slave mode after reset.
4.3
Temporary Master Mode
The CPS-16/12/8 supports temporary Master mode to directly obtain its configuration from an external
EEPROM using I
2
C. As such, in Master mode the device can read/download, and optionally verify, its
registers from an external EEPROM. The CPS-16/12/8 will operate one burst read to download all data
from EEPROM. I
2
C burst read start address 0xh00 (16bit address bit).
The device supports configuration into temporary Master mode in two ways:
1. If an external Master mode signal is tied to V
DD
(1.2V), the device will come out of reset in Master mode.
2. If the Master mode signal is left floating the device will come out of reset in Slave mode, but can be
configured to transition to Master mode. This is done by setting I2C frequency, slave address, and
checksum disable in I2C Master Control Register and I2C Master Status and Control Register.
4.3.1
Obtaining Configuration in Master Mode
If the Master mode signal, MM, is tied to V
DD
(1.2V), the CPS-16/12/8 will attempt to load its configuration
registers after the device reset sequence has completed. The CPS-16/12/8 uses a 7-bit address of
1010[ID2][ID1][ID0] as the slave address of the device from which it will obtain its configuration.
[ID2][ID1][ID0] are external signals to the device, and are the same three lower bits that would be used for
the device’s I
2
C address when configured as a slave. When configured to come out of reset as an I
2
C
master, the device supports communication only with an external device that has a 7-bit address. 10-bit I
2
C
addressing is not supported in this mode. The data includes a CRC value that the CPS-16/12/8 uses to
compare against its own calculated value to determine the validity of the registers load. The registers are
loaded from the EEPROM regardless of the value of the checksum, but a flag is set (I2C Master Status and
Control Register.I2C_CHKSUM_FAIL) if the CRC fails.
