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Revision 1.5

Integrated Device Technology, Inc.

CPS-16/12/8 User Manual

6 - 1

July 10, 2012

Chapter 6

JTAG & Boundary Scan

6 JTAG & BOUNDARY SCAN

The CPS supports all the mandatory instructions defined in the IEEE 1149.1 specification. To support
production testing, the device supports private instructions for Memory BIST and Scan Testing. The TAP
controller allows access to the configuration registers. Boundary scan testing of the AC-coupled IOs are
performed in accordance with IEEE 1149.6 (AC Extest).
This chapter covers the overall functionality of the JTAG TAP port interface and Configuration Registers
Access (CRA) capability. For the full specification, please refer to the device’s datasheet.

6.1 JTAG AND AC EXTEST COMPLIANCE

All DC pins are in full compliance with IEEE 1149.1. All AC-coupled pins fully comply with IEEE 1149.6. All
1149.1 and 1149.6 boundary scan cells are on the same chain. No additional control cells are provided for
independent selection of negative and / or positive terminals of the Tx or Rx pairs.

6.2 TEST INSTRUCTIONS

The CPS-16/12/8’s JTAG functionality does not support register access when it is part of a chain,
and must be the only device on the JTAG bus when its registers are accessed using JTAG
interface.

Table 6.1 Test Instructions

IR Code [3:0]

Instruction

Comments

0x0

Ex_Test

Implemented per IEEE 1149.1-2001

0x1

Sample/Preload

Implemented per IEEE 1149.1-2001

0x2

ID Code

Implemented per IEEE 1149.1-2001
Device ID = 0x35B (CPS-16)
Device ID = 0x25C (CPS-8)

0x3

High Z

Implemented per IEEE 1149.1-2001

0x4

Clamp

Implemented per IEEE 1149.1-2001

0x5

Ex_Test Pulse

Implemented per IEEE 1149.6

0x6

Ex_Test Train

Implemented per IEEE 1149.6

0x7

Reserved

0x8

Reserved

0x9

Reserved

0xA

Configuration Register

Access

Read and Write Access to Configuration Register space

0xB

ISCAN

Enables internal Scan for production test

0xC

Reserved

0xD

Reserved

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52
53
54
55
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Summary of Contents for CPS-12

Page 1: ...July 10 2012 IDT CPS 16 12 8 Central Packet Switch User Manual Revision 1 5 Tit ...

Page 2: ...on request Items identified herein as reserved or undefined are reserved for future definition IDT does not assume responsibility for conflicts or incompatibilities arising from the future definition of such items IDT products have not been designed tested or manufactured for use in and thus are not warranted for applications where the failure malfunction or any inaccuracy in the application carri...

Page 3: ...ents 3 1 3 3 Switch Description 3 2 3 4 Switching Scheduler and Priorities 3 3 3 5 Flow Control and Congestion Management 3 5 4 I2C Interface 4 1 4 1 Overview 4 1 4 2 Master Slave Configuration 4 1 4 3 Temporary Master Mode 4 1 4 4 Slave Mode 4 7 5 Error Management 5 1 5 1 Error Management Functional Architecture 5 1 6 JTAG Boundary Scan 6 1 6 1 JTAG and AC Extest Compliance 6 1 6 2 Test Instructi...

Page 4: ...egisters 10 1 10 1 RapidIO Compliance 10 1 10 2 Register Type Field Definitions 10 1 10 3 Address Map 10 2 10 4 Rapid IO Registers 10 8 10 5 RIO extended feature registeR 10 19 10 6 IDT Specific sRIO Extended Feature Set 10 24 10 7 Routing Table Registers 10 25 10 8 Trace Registers 10 26 10 9 Global Configuration Registers 10 31 10 10 Multicast Registers 10 38 10 11 Switching Port Registers 10 40 ...

Page 5: ...Figure 4 7 Combined Format 4 10 Figure 4 8 Master Addresses a Slave Receiver with 10 bit Address 4 10 Figure 4 9 Master Addresses a Slave Transmitter with 10 bit Address 4 10 Figure 4 10 Combined Format Master Addresses a Slave with 10 bit Address 4 10 Figure 4 11 Combined Format Master Transmits Data to Two Slaves Both with 10 bit Address 4 11 Figure 4 12 Write Protocol with 10 bit Slave Address ...

Page 6: ...tenance Response Packet generated by CPS 8 2 Table 8 3 Port Configuration 8 4 Table 8 4 Multicast Mask Register References for Multicast Mask Port CSR Usage 8 6 Table 8 5 Region Select 8 7 Table 8 6 Port Number References 8 7 Table 8 7 Multicast Mask References 8 8 Table 9 1 Port Configuration at Power Up 9 1 Table 9 2 Default Speed Settings with SPD0 and SPD1 9 2 Table 10 1 Register Types 10 1 Ta...

Page 7: ...ONF_MOD_ERR_REPORT_ENABLE 0xF20014 10 32 Table 10 46 AUXPORT_ERR_REPORT_ENABLE 0xF20018 10 33 Table 10 47 MAINT_ERR_REPORT_ENABLE 0xF2001C 10 33 Table 10 48 RIO_DOMAIN 0xF20020 10 33 Table 10 49 RIO_PORT_WRITE_INFO 0xF20024 10 34 Table 10 50 RIO_PORT_WRITE_SRCID 0xF20028 10 34 Table 10 51 RIO_ASSY_IDENT_CAR 0xF2002C 10 35 Table 10 52 RIO_ASSY_INF_CAR 0xF20030 10 35 Table 10 53 PPS_SOFT_RESET 0xF20...

Page 8: ...PECIAL_ERR_0 0xFD0008 10 48 Table 10 78 ERR_FLAG 0xFD0028 10 50 Table 10 79 ERR_COUNTER 0xFD002C 10 50 Table 10 80 ERR_RESET 0xFD0030 10 51 Table 10 81 QUAD_CTRL Control Register Map 10 52 Table 10 82 QUAD_0_CTRL 0xFF0000 10 52 Table 10 83 QUAD_0_ERR_REPORT_EN 0xFF0004 10 54 Table 10 84 QUAD_CTRL_BROADCAST 0xFFF000 10 54 ...

Page 9: ...and responding to error reports from all of the functional blocks within the device Chapter 6 JTAG Boundary Scan describes the CPS JTAG interface and code Chapter 7 Reference Clock describes the reference clock requirement system clock and SerDes clock generation Chapter 8 Programming the CPS provides the basic configure steps and rules Chapter 9 CPS Reset Initialization provides reset and init st...

Page 10: ...e read but not modified A sticky bit is a bit that remains set after being set by hardware until a zero is written to it Writing a one to a sticky has no effect on its value A zero field in a register denoted as 0 in register figures must be written with a value of zero and returns a value of zero when read Revision History July 10 2012 Revision 1 5 Removed the confidential statements from the doc...

Page 11: ...IO specifi cations In addition the device supports lane grouping in an enhanced mode such that a group of 4 Lanes can be configured as four individual non redundant 1x ports The CPS device supports the reception of SRIO maintenance packets type 8 which are directed to it i e hop count of 0 in support of requirements defined for a RIO switch in the applicable version 1 3 Rapid IO specifications The...

Page 12: ...ast control symbol Support Broadcast 10 Multicast mask Per port independent routing table Packet Trace Each Port provides the ability to match the first 160 bits of any packet against up to four program mable values as comparison criteria to copy the packet to a programmable output trace port Clock and reset Single input reference clock Global hardware reset Software reset Diagnostic packet counte...

Page 13: ...AG I2C SRIO Quad 0 Logical SRIO SERDES Lane 0 SRIO SERDES Lane 1 SRIO SERDES Lane 2 SRIO SERDES Lane 3 SRIO Quad 1 Logical SRIO SERDES Lane 4 SRIO SERDES Lane 5 SRIO SERDES Lane 6 SRIO SERDES Lane 7 SRIO Quad 2 Logical SRIO SERDES Lane 8 SRIO SERDES Lane 9 SRIO SERDES Lane 10 SRIO SERDES Lane 11 SRIO Quad 3 Logical SRIO SERDES Lane 12 SRIO SERDES Lane 13 SRIO SERDES Lane 14 SRIO SERDES Lane 15 ...

Page 14: ...er less chain can be done by a fast non blocking switch It s also suitable in processing card since more and more processing is moved from RNC to Node B in the emerging applica tions The CPS provides direct support for backplane connections using the serial RapidIO standard The addition of an appropriate bridge e g CPRI to sRIO allows for further backplane flexibility accommodating designs based o...

Page 15: ...e CPS family device provides 16 12 8 sRIO lanes which can be configured into up to 16 12 8 ports The 80KSW0001 provides up to 12 ports 1 7 3 Bandwidth CPS provides a 40 30 20 Gbps bandwidth 1 7 4 PPSc Capability The CPS family does not have PPSc 1 7 5 I2 C Interface The CPS I2 C interface may work either in Master mode or Slave mode 1 7 6 Broadcast and Broadcast Packet Filtering The CPS support br...

Page 16: ...s the ability for each of its four lanes to be used as individual 1x ports 1 lane per port When configured into standard mode the quad is usable as a single 4x port 4 sRIO lanes or as a 1x port When an enhanced quad s lanes are being used as four individual 1x ports redundancy as defined by the sRIO specification is not provided An Enhanced Quad can be configured into either enhanced or standard m...

Page 17: ...RapidIO Specifications revision 1 3 2 1 3 Lane Configuration SRIO lane characteristics is configurable via a set of QUAD_n_CTRL registers These characteristics include the following Data Rate Transmitter Pre emphasis Drive Strength For the CPS device control of each of these parameters are separately configurable such that the charac teristics for lanes 0 and 1 can be different from those for land...

Page 18: ... control symbol will be transmitted within the packet i e within the boundary of the packet s SOP and EOP until the rest or more of the packet becomes available for transmission Cut Through is disabled at reset of the device This mode is enabled globally via a maintenance write command to the CUT_THRU_ENABLE bit of the CPS_CONTROL register If this bit is set Cut Through forwarding methodology will...

Page 19: ... value mask is used as a don t care A don t care value results in an automatic match of the corresponding bits in the programmable value with the corresponding packet data bits When all bits of the packet data match with a given corresponding bit in a given programmable value after the value s mask has been applied the Trace criteria has been met and the packet is forwarded to the trace enabled ou...

Page 20: ...e routed to the trace port 2 2 2 Trace Output Port Features At any given time the device supports a single Trace enabled output port It can be dynamically defined which output port is enabled for the Trace function All packets which match the Trace Criteria from all trace enabled inputs is routed to the same configured trace output port The device supports the ability for the port defined as the o...

Page 21: ...ns Packets which meet the trace criteria are routed to the trace port even if the packet destination ID reference in the port s route table indicates no route 2 2 4 Trace Function Dynamic Programmability By offering dynamic configurability the CPS device provides the user with the ability to modify trace func tion parameters without disabling the normal operation of the port s functionality The us...

Page 22: ...ria had a hop count of 0 The device supports the ability for the packet filtering to be enabled disable at each port individually for each unique comparison value at that port The device provides the ability to enable disable packet trace and packet filtering simultaneously for each port individually for each unique comparison value at that port If both packet filtering and packet trace are enable...

Page 23: ...ate it will return to the normal operational state after updating the expected ID value If a packet is being received during this transition it will be dropped without response 2 4 4 3 OUTBOUND ACKID CPS supports both reads from and writes to the OUTBOUND_ACKID parameter If read CPS will refer to the value that the device will use for the next transmitted packet ack If written the effect will be d...

Page 24: ...h with a maximum 2 5Gb s data bandwidth the PVCs connected to that quad supports all 4 ports by granting bandwidth to each port in 32bit word portions It is this time sharing concept that is the origin of many of the sub modules that refer to time divi sion multiplexing TDM in regard to PVC operation This TDM method is strictly per PVC and is not func tional as an overall switch wide time division...

Page 25: ...er space is 3 maximum size packet for priority 0 2 maximum sized packets for priority 1 and 1 maximum sized packet for priority 2 and 3 but this is subject to change by user The input buffer simply provides a temporary storage for incoming packets and absorbs the burst For maintenance packet the buffer size is 88Bytes per priority per port Separate maintenance packet input buffer will avoid being ...

Page 26: ... per port Each output buffer can track up to 3 packets given that there is enough buffer space for them The output buffer will only allow new packet in if it has free tracking resources and buffer space available for a full maximum sized packet For maintenance packet path the buffer size is 88 bytes per priority per port The separate maintenance packet buffer forms an independent data path 3 3 5 R...

Page 27: ...ch reach the port bandwidth then the lower priority packet will continuously hold off until higher priority packet bandwidth drop below the port bandwidth The same rule apples to all ports Also the following behavior is standard 1 Not blocking with the same priority If rx port B receives a packet call it PC of priority M where M N targeted for tx port A but port A cannot receive it due to the conf...

Page 28: ...rable even at the cost of occasional packet loss It is implemented by not storing packets in the retransmit buffer In this way if a retry was received because the link partner has a full input buffer or if a NAK was received because of a transmission error then CPS would simple resent the next available packet instead of retransmitting the previous one RT mimic affects behavior on the output port ...

Page 29: ...12 8 will operate one burst read to download all data from EEPROM I2C burst read start address 0xh00 16bit address bit The device supports configuration into temporary Master mode in two ways 1 If an external Master mode signal is tied to VDD 1 2V the device will come out of reset in Master mode 2 If the Master mode signal is left floating the device will come out of reset in Slave mode but can be...

Page 30: ...orary Master mode the state of the external ADS signal is ignored Once the device completes its configuration sequence successfully or unsuccessfully it reverts to slave mode where the ADS signal will become active 4 3 3 Master Clock Frequency While in the Master mode the CPS 16 12 8 can be configured to supply a clock of either 100 kHz Standard mode or 400 kHz Fast mode 4 3 4 Register Map The dev...

Page 31: ... a 16 bit value that defines the total number of configuration blocks to read 0 7 0x0003 0 7 Second byte of a 16 bit value that defines the total number of configuration blocks to read 8 15 For n configuration blocks the value entered here is n 1 0x0004 0 7 The lower 8 bits of a 10 bit value that defines the number of words in configuration Block 1 Represents bits 0 7 of the 10 bit block count For...

Page 32: ...t do that therefore the standard CRC 16 algorithm will not generate a correct CRC The following algorithm will generate the CRC 16 expected at the end of the EEPROM unsigned short icrc16 unsigned char data int numBytes unsigned short remainder 0 unsigned char crc 16 unsigned char byte unsigned char bit_Pos unsigned char bit_Pos_Mask unsigned char carry unsigned char serial_data unsigned int word i...

Page 33: ...f i 0 crc i carry serial_data else crc i crc i 1 bit_Pos_Mask 1 for i 15 i 0 i remainder crc i i return remainder 4 3 6 Register Map Example The following is a list of registers to be configured through an I2C EEPROM and the I2C values required to set those registers Table 4 2 Register Map Example Register Value Comment 0x00015C 0x00600000 Block 1 0xE00000 0x01 Block 2 0xE00004 0x02 0xE00008 0x03 ...

Page 34: ...ount 1 0x0005 0x00 0x0006 0x00 0x0007 0x57 Address 0x158 2 0x57 0x0008 0x00 Data for block 1 0x00600000 0x0009 0x06 0x000A 0x00 0x000B 0x00 0x000C 0x08 Start of Block 2 Register count 9 0x000D 0x38 Address 0xE00000 2 0x380000 0x000E 0x00 0x000F 0x00 0x0010 0x01 Data for address 0xE00000 0x0011 0x02 Data for address 0xE00004 0x0012 0x03 Data for address 0xE00008 0x0013 0x04 Data for address 0xE0001...

Page 35: ...es as a 7 bit addressable device as defined by ID 6 0 0x0017 0x08 Data for address 0xE00020 0x0018 0x09 Data for address 0xE00024 0x0019 0x00 Start of Block 3 Register count 1 0x001A 0x00 Address 0x6c 2 0x1B 0x001B 0x00 0x001C 0x1B 0x001D 0x00 Data for address 0x6c 0x00000014 0x001E 0x00 0x001F 0x00 0x0020 0x14 0x0021 0xD7 CRC 0xD746 0x0022 0x46 Table 4 4 I2 C Address Pins Pin Name ID 9 I2C addres...

Page 36: ...nds data to the CPS 16 12 8 slave receiver c Master device terminates the transfer 2 CPS 16 12 8 to Master device a Master device addresses the CPS 16 12 8 slave b Master device master receiver receives data from the CPS 16 12 8 slave transmitter c Master device terminates the transfer Full signaling definition is defined in the I2C Specification Standard waveforms are displayed in the following f...

Page 37: ...logy Inc CPS 16 12 8 User Manual 4 9 July 10 2012 Figure 4 3 Data Transfer Figure 4 4 Acknowledgment Figure 4 5 Master Addressing a Slave with a 7 bit Address Transfer Direction is Not Changed Figure 4 6 Master Reads a Slave Immediately After the First Byte ...

Page 38: ... 10 2012 Figure 4 7 Combined Format Figure 4 8 Master Addresses a Slave Receiver with 10 bit Address Figure 4 9 Master Addresses a Slave Transmitter with 10 bit Address Figure 4 10 Combined Format Master Addresses a Slave with 10 bit Address1 1 Then transmits data to slave and reads data from slave ...

Page 39: ... CPS 16 12 8 will respond accordingly even when the slave address is set to specification reserved address ranges As a slave the CPS 16 12 8 read procedure has the memory address section of the transfer removed To perform a read the proper access will be to perform a write operation which provides a 22 bit address and then to issue a repeated start after the acknowledge bit following the third byt...

Page 40: ...24 Input Data 23 16 Input Data 15 8 Input Data 7 0 A ACK 73 82 92 55 64 A 1 ACK R W R 1 W 0 Device Address 9 8 1 1 1 1 0 S A Sr repeated START DATA A ACK A ACK DATA DATA A ACK DATA _ A P STOP Output Data 31 24 Output Data 23 16 Output Data 15 8 Output Data 7 0 27 36 45 A 0 ACK R W 0 S START 9 R 1 W 0 Device Address 9 8 SLAVE ADDR A ACK 1 1 1 1 0 S A Device Address 7 0 18 Memory Address 23 18 Memor...

Page 41: ...55 64 73 83 Memory Address 23 18 Memory Address 17 10 Memory Address 9 2 27 36 18 SLAVE ADDR A 0 ACK R W 0 S START 9 R 1 W 0 Device Address 6 0 DATA A ACK A ACK DATA DATA A ACK DATA A ACK A ACK DATA DATA A ACK DATA _ A P STOP NACK _ A Output Data 31 24 Output Data 23 16 Output Data 15 8 Output Data 7 0 Sr repeated START SLAVE ADDR A 1 ACK R W R 1 W 0 Device Address 6 0 ...

Page 42: ...t supports error reporting capability is defined as an Error Source The device supports the ability for the user to enable and disable the error reporting functionality of each of these sources Regardless of whether or not reporting is enabled all errors that are received by the Error Management Block will be stored to the Error Log The listing of Error Sources and their respective codes is provid...

Page 43: ...he Error Log This is a 32 bit register which lists the location and type of error Error Source Error Code 14 bits that occurred When this register is read the device returns the first entry in the Error Log The device provides the user with the ability to reset the contents of Error Log FIFO and the Error Log Read Register 5 1 1 1 I2 C Errors The I2C errors shown in the table below are detectable ...

Page 44: ...e all three bytes of a memory address are received This occurs when the device is in slave mode and being addressed by the Master I2C device The memory address will not be updated and the write opera tion will be aborted Unexpected START STOP 0x13 This error is captured when as a slave the device encounters an unexpected START or STOP When this happens during addressing or during a mem ory address...

Page 45: ...es A response packet with an error status will be generated Maintenance Write Size Invalid 0x32 Triggered when a write request maintenance packet has an invalid size i e not 8 16 32 or 64 bytes A response packet with an error status will be generated Maintenance Transaction Field Error 0x33 An unexpected transaction field was decoded in an inbound maintenance packet with hop count 0 Maintenance re...

Page 46: ...t multicast masks Reads of invalid values also trigger this error Port config error 0x53 Triggered when a direct write to a route table is attempted with an invalid PORT number A NO_ROUTE will be written into the route table instead This is also triggered whenever the mcast_msk_port_csr is written to that contains an invalid egress port number This error is also triggered when an attempt is made t...

Page 47: ...st 0x62 Triggered when Lane 2 of a given quad has lost sync Reported only when quad_err_report is enabled Lane 3 Sync Lost 0x63 Triggered when Lane 3 of a given quad has lost sync Reported only when quad_err_report is enabled Alignment Lost 0x64 Triggered when lane alignment has been lost when a port is in 4x mode Reported only when quad_err_report is enabled Table 5 7 RIO Link Layer Errors and Co...

Page 48: ...alization This error will only be detected when the output side of the port transmitter reacquires the port init signal after having lost it It will not be detected when initialization is first acquired after power up or disabling and re enabling the port of following a soft reset event It will be detected only when initialization is lost during the normal exchange of pack ets and control symbols ...

Page 49: ...0x90 Triggered when a packet is received which exceeds the RIO length maximum 69 words Reported only when Port error reporting is enabled Invalid transaction type 0x91 Triggered when a packet is received with an invalid tt field Reported only when Port error reporting is enabled Pri 0 Rx buffer over flow 0x92 Triggered when the priority 0 packet buffer encounters an over flow condition Reported on...

Page 50: ...flag bits are de asserted The Error Flag Register will be reset when the Error Management module is reset or the Error Flag bit in Error Reset Register is set 5 1 2 3 Error Interrupt The device provides a single open drain interrupt pin Its output state is driven by the logical OR of all Error Flag Register bits such that if any one of the error flag bits are set the Interrupt pin is driven to its...

Page 51: ... STOP_EM bit in the Error Reset Register when the Error Counter value reaches 0xFF thus stopping the Error Manager A maintenance packet is generated and transmitted if this sequence occurs under these configuration conditions 5 1 2 7 Error Reset The device provides an Error Reset Register which allows the user to reset the Error Flag Register the Error Counter and or the Error Log This register al...

Page 52: ...fined in the register RIO_PORT_WRITE_SRCID the size is determined by the value of the LARGE_TRANS field in the RIO_PORT_WRITE_INFO register vi ttype transaction 0b0100 vii rdsize wrsize 0b1011 viii Hop_Count 0xFF ix W wptr 0b0 Table 5 10 Port Write Payload Definition Reserved Error Source Error Code Error Flags Error Counter Reserved 00 6 bit 8 bits 8 bits 16 bits 00000000000000000000000 Table 5 1...

Page 53: ...9 1 and 1149 6 boundary scan cells are on the same chain No additional control cells are provided for independent selection of negative and or positive terminals of the Tx or Rx pairs 6 2 TEST INSTRUCTIONS The CPS 16 12 8 s JTAG functionality does not support register access when it is part of a chain and must be the only device on the JTAG bus when its registers are accessed using JTAG interface ...

Page 54: ...nimum to reset the controller To deactivate JTAG TRST is tied low so that the TAP controller remains in a known state at all times All of the other JTAG input pins are internally biased in such a way that by leaving them unconnected they are automatically disabled Note that JTAG inputs are OK to float because they have leakers as required by IEEE 1149 1 specification 6 5 CONFIGURATION REGISTER ACC...

Page 55: ...tag_config_addr TDI is not used after the address is shifted in Timing is shown below Figure 6 2 JTAG Read Access 6 6 BOUNDARY SCAN JTAG instructions are provided for the purpose of making all the part inputs observable and all the outputs controllable All external I Os are designed to support Boundary Scan testing as defined in IEEE 1149 1 and 1149 6 converting digital and AC coupled I Os respect...

Page 56: ...ality when supplied with a reference clock of 156 25 MHz Figure 7 1 Reference Clock Representative Circuit 7 2 PLL The device provides an internal PLL to create the 312 5MHz or half of that internal SYS_CLK that is used to drive internal logic The REF_CLK is multiplied by 4 8 and 10 to generate the bit clocks needed for PHY clocks The resultant PHY_CLK is also divided by 5 for the byte time of the...

Page 57: ...y Inc CPS 16 12 8 User Manual 7 2 July 10 2012 Figure 7 2 Internal PLL Clock Generator System Clock PLL REF_CLK SYS_CLK 312 MHz PHY PLL PHY_CLK 625 MHz Byte_CLK 125 MHz PHY_CLK 1 25 GHz Byte_CLK 250 MHz PHY_CLK 1 56 GHz Byte_CLK 312 MHz x4 x8 x10 x4 5 x8 5 x10 5 ...

Page 58: ... the CPS functions per the RapidIO specifications as a switch It identifies a Maintenance Packet by decoding the ftype field to be 0b1000 The CPS decodes the RIO defined hop_count field of the Maintenance Packet If it has the value of 0 the CPS terminate and process the packet If the hop_count field is greater than 0 the CPS decrements the value by 1 recalculate the CRC and forward the packet to t...

Page 59: ...y was 3 then the response will be kept at priority 3 3 destinationID uses the value of the request packet s sourceID field 4 sourceID uses the value of the request packet s destinationID field 5 transaction is set to the correct response type as defined in the RIO specification 6 status is always set to 0b0000 7 hop_count is set to 0xFF 8 read data as requested is provided in response packets The ...

Page 60: ...2 3 Individual Local Route Tables Access In addition to the ability to globally access the routing tables the CPS provides the user with the ability to write and read each individual port s local route tables both device and domain This provides the user with the ability to route packets with the same destination ID if received on different ports to different output destination A write to an indiv...

Page 61: ...te table with the lower 8 bits config_destID is forced If the destination ID is only 8 bits CPS uses these 8 bits as a direct address offset into the route table to obtain its forwarding information 8 2 5 Route Table Programming The CPS device allows the user access to each of the tables via RIO type 8 maintenance commands as defined in the RIO Part 1 rev 1 3 specification The CPS provides the use...

Page 62: ... Specification The Standard Route Configuration destination ID Select CSR specifies the destination ID entry in the switch routing table to access when the Standard Route Configuration Port Select CSR is read or written Block writes i e writing four consecutive entries into the route table are also supported In the case of a block write if the 8 MSBs of a 16 bit destination ID do not match the val...

Page 63: ... its 10 multicast mask registers indirectly through use of the Multicast Mask Port CSR the Multicast Associate Select CSR and the Multicast Associate Operation CSR as defined in RapidIO Interconnect Specification Part 9 Multicast Extensions Specification The CPS supports the use of a Multicast Mask Port CSR as defined in RIO Part 9 in order to assign ports to multicast mask registers It supports m...

Page 64: ...r to properly map packets to the proper device construct the user must use the route table values defined below 8 2 7 1 Direct Output Port Mapping Packets are routed directly to output ports in a unicast fashion To configure the device for this type of func tionality the values in the table below is used 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 9 Table 8 5 Region Select A7...

Page 65: ...ast Mask Register addresses are supported in the Device Route Table but not in the Domain Route Table 8 2 7 3 Default Route The CPS supports references to its default port in both its Device Route Table and its Domain Route Table The default value of routing table is 0xDE for all destination ID 0xDE means route packet to the default port The default port can be programmable through Standard Defaul...

Page 66: ...es two options that define the behavior of the CPS when this control symbol is received from one of the RIO ports The user can program the ENABLE_PORT_RESET field in CPS_CONTROL register If this bit is set to 0 the whole device will be reset upon receipt of a reset symbol Otherwise it will reset the port on which the symbol was received 8 3 2 Per Port Reset Per Port reset is reset to a single port...

Page 67: ...e This lockout counter is cleared by a local soft reset event 14 There is a symbol counter in the output side of the port that counts the number of link request reset device control symbols for the port to transmit when the port s link maintenance response CSR is written with a request to send a link reset sequence This symbol counter is cleared by a local soft reset event 15 There is a symbol que...

Page 68: ...ll lanes will be disabled which will force loss of link with the lane partner This will cause link re negotiation to occur in the same way as if the force_reinit function had been invoked 8 3 3 Reset Configuration After resetting the CPS the ports are set to their default configuration with the port speed dictated by the speed pins refer to the Reset Initialization chapter Since the serial RapidIO...

Page 69: ...configuration of the physical layer of all CPS ports This is key to configuring the device to interface properly to adjacent devices in the system prior to any sRIO bring up and initialization routines take place Anytime a quad is configured or reconfigured the user must also reinitialize the link by writing to the FORCE_REINIT field in the QUAD_CTRL register See the Registers chapter for more det...

Page 70: ...outes in the route table Multiple number of routes can be entered which will be either deleted or inserted If a route can not be added the function is terminated and index of unsuccessful route is returned Status_destID This function checks if a destID is in the route table Write_Domain_Register This function can be used to directly write into the domain register instead of indirectly accessing it...

Page 71: ... 9 1 1 RIO Ports After Power Up and after device reset the RIO Port configuration is as defined below Table 9 1 Port Configuration at Power Up Lane Port Mode Port Number CPS 8 0 Enhanced 1x 0 1 Enhanced 1x 1 2 Enhanced 1x 2 3 Enhanced 1x 3 4 Enhanced 1x 4 5 Enhanced 1x 5 6 Enhanced 1x 6 7 Enhanced 1x 7 CPS 12 8 Enhanced 1x 8 9 Enhanced 1x 9 10 Enhanced 1x 10 11 Enhanced 1x 11 CPS 16 12 Enhanced 1x...

Page 72: ...cation long run short run These registers are programmable through the I2C or JTAG interfaces during system initialization as well 9 4 RIO SYSTEM BRING UP The device supports the system bring up requirements defined in the RapidIO System Interconnect Spec ification Annex 1 Software and System Bringup Specification 9 5 SERDES INITIALIZATION SERDES Initialization for the CPS is defined in Chapter 6 ...

Page 73: ...ster as only being applicable to end points 10 1 1 Interpretation of Reserved Register Bits The CPS design is based on the RIO definition for the treatment of reserved register bits to support compat ibility with the existing PPS Gen 2 device 80KSW0001 This treatment is defined in Table 3 2 of the RIO Common Transport Specification Part 3 Under the Target Behavior column the expected return of the...

Page 74: ...x000004 DEV_INF_CAR 0x000008 ASSY_IDENT_CAR 0x00000C ASSY_INF_CAR 0x000010 PROC_ELEM_FEAT_CAR 0x000014 SWITCH_PORT_INF_CAR 0x000018 SRC_OP_CAR 0x000030 SW_MCAST_SUP_CAR 0x000034 SW_RTE_TBL_LIM_CAR 0x000038 SW_MCAST_INF_CAR 0x000068 HOST_BASE_DEV_ID_LOCK_CSR 0x00006C COMP_TAG_CSR 0x000070 STD_RTE_CONF_DESTID_SEL_CSR 0x000074 STD_RTE_CONF_PORT_SEL_CSR 0x000078 STD_RTE_DEF_PORT_CSR 0x000080 MCAST_MSK...

Page 75: ...0400 Global Domain Route Table 0xE10000 Port 0 Device Route Table 0xE10400 Port 0 Domain Route Table 0xE10000 0x1000 PORT_ NUM Registers start for port PORT_NUM 0xE1F000 Port 15 Domain Route Table 0xE1F400 Port 15 Device Route Table 0xE40000 E4B08C Trace Comparison Values and Masks 0xE40000 Port 0 Trace Comparison Value 1 0xE40014 Port 0 Trace Mask 1 0xE40028 Port 0 Trace Comparison Value 2 0xE400...

Page 76: ...ce Mask 2 0xE4FF50 Broadcast Trace Comparison Value 3 0xE4FF64 Broadcast Trace Mask 3 0xE4FF78 Broadcast Trace Comparison Value 4 0xE4FF8C Broadcast Trace Mask 4 0xF00000 0xF1FFFF Vendor access only 0xF20000 0xF20100 Global Configuration Registers 0xF20000 0xF20008 Reserved 0xF2000C CPS_CONTROL 0xF20010 Vendor access only 0xF20014 CONF_MOD_ERR_REPORT_ENABLE 0xF20018 AUXPORT_ERR_REPORT_ENABLE 0xF20...

Page 77: ...gisters 0xF40000 PORT_0_BUF_SIZE 0xF40004 PORT_0_OPS 0xF40008 PORT_0_ERR_REPORT_ENABLE 0xF4000C PORT_0_SWITCH_BUF_STATUS 0xF40010 PORT_0_ACK_CNTR 0xF40014 PORT_0_NACK_CNTR 0xF40018 Reserved 0xF4001C PORT_0_SW_PKT_CNTR 0xF40020 PORT_0_TRACE_MATCH_CNTR_1 0xF40024 PORT_0_TRACE_MATCH_CNTR_2 0xF40028 PORT_0_TRACE_MATCH_CNTR_3 0xF4002C PORT_0_TRACE_MATCH_CNTR_4 0xF40030 PORT_0_FILTER_MATCH_CNTR_1 0xF400...

Page 78: ...15_FILTER_MATCH_CNTR_1 0xF40F34 PORT_15_FILTER_MATCH_CNTR_2 0xF40F38 PORT_15_FILTER_MATCH_CNTR_3 0xF40F3C PORT_15_FILTER_MATCH_CNTR_4 0xF4FF00 0xF4FF08 Broadcast to Switchport Registers 0xF4FF00 PORT_BUF_SIZE_BROADCAST 0xF4FF04 PORT_OPS_BROADCAST 0xF4FF08 PORT_ERR_REPORT_ENABLE_BROADCAST 0xF50000 Vendor access only 0xFD0000 0xFD0030 Error Handling Registers 0xFD0000 ERR_CAP_REG 0xFD0004 ERR_LOG 0x...

Page 79: ...0 ERR_RESET 0xFF0000 0xFFF000 Quad Control Registers 0xFF0000 QUAD_0_CTRL 0xFF0004 QUAD_0_ERR_REPORT_EN 0xFF1000 QUAD_1_CTRL 0xFF1004 QUAD_1_ERR_REPORT_EN 0xFF2000 QUAD_2_CTRL 0xFF2004 QUAD_2_ERR_REPORT_EN 0xFF3000 QUAD_3_CTRL 0xFF3004 QUAD_3_ERR_REPORT_EN 0xFFF000 QUAD_CTRL_BROADCAST Table 10 2 CPS Memory Map Base Address Description ...

Page 80: ... Name Type Reset Value Comment 15 0 DEV_VENDOR_IDENT FR 0x0038 Device Vendor Identifier Assigned by the RTA specifically for IDT 31 16 DEV_IDENT FR 0x35B 0x35C 0x35D Specific Device Identifier 0x35B is for the 16 port version 0x35C is for the 8 port version 0x35D is for the 12 port version Table 10 4 DEV_INF_CAR 0x000004 Bit Field Name Type Reset Value Comment 3 0 DEV_REG_JTAG FR 0b0000 Device Rev...

Page 81: ...dentifier This field is used to uniquely identify the manufactur ing vendor of the assembly containing this device 31 16 ASSY_IDENT FR 0x0000 This field uniquely identifies the type of assembly used Assigned by the assem bly supplier The reader is referred to the definition of the RIO_ASSY_IDENT_CAR Table 10 6 ASSY_INF_CAR 0x00000C Bit Field Name Type Reset Value Comment 15 0 EXT_FEAT_PTR FR 0x010...

Page 82: ...bit source and destination IDs 1 enabled 5 CRITICAL_REQUEST_FLOW_SU PPORT FR 0b0 0 Critical Request Flow not sup ported 1 Critical Request Flow is sup ported 6 CRC_ERROR_RECOVERY FR 0b1 0 Suppression of error recovery on CRC error is not supported 1 Suppression of error recovery on CRC error is supported 7 Reserved 8 STANDARD_ROUTE_CONFIGUR ATION_SUPPORT FR 0b1 The device supports the standard rou...

Page 83: ...may or may not be able to bridge between sRIO and another non sRIO interface 0 No support for bridging to a non sRIO interface Table 10 8 SWITCH_PORT_INF_CAR 0x000014 Bit Field Name Type Reset Value Comment 7 0 PORT_NUMBER RO 0x00 The port number from which the mainte nance read operation accessed this register For I2C accessed value is 0xFE 15 8 PORT_TOTAL RO 0x10 0x0B 0x08 The total number of po...

Page 84: ... yes 5 ATOMIC_SET FR 0b0 Defines the ability of the device to support an atomic set operation 0 no 1 yes 6 ATOMIC_DECREMENT FR 0b0 Defines the ability of the device to support an atomic decrement oper ation 0 no 1 yes 7 ATOMIC_INCREMENT FR 0b0 Defines the ability of the device to support an atomic increment opera tion 0 no 1 yes 8 ATOMIC_TEST_AND_SWAP FR 0b0 Defines the ability of the device to su...

Page 85: ...ines the ability of the device to support a streaming write operation 0 no 1 yes 14 WRITE FR 0b0 Defines the ability of the device to source a write operation 0 no 1 yes 15 READ FR 0b0 Defines the ability of the device to source a read operation 0 no 1 yes 31 16 Reserved Table 10 10 SW_MCAST_SUP_CAR 0x000030 Bit Field Name Type Reset Value Comment 30 0 Reserved 31 SIMPLE_ASSOC FR 0b0 Defines the d...

Page 86: ...IDs that are supported 0xFF 256 31 16 Reserved Table 10 12 SW_MULT_INF_CAR 0x000038 Bit Field Name Type Reset Value Comment 15 0 MULTICAST_MASKS FR 0x000A Defines the number of multicast mask that are supported by the device 29 16 MAXIMIM_DESTINATION_IDS_ PER_MULTICAST_MASK FR 0x00FF The max number of destination IDs that can be associated with a multicast mask 30 PER_PORT_ASSOCIATION FR 0b0 Per I...

Page 87: ...10 14 COMPONENT_TAG_CSR 0x00006C Bit Field Name Type Reset Value Comment 31 0 COMPONENT_TAG R W 0x00 Component Tag for this device Table 10 15 STD_RTE_CONF_DESTID_SEL_CSR 0x000070 Bit Field Name Type Reset Value Comment 7 0 CONF_DESTID R W 0x00 Defines the destination ID used to select an entry in the switch routing table 15 8 LARGE_CONFIG_DESTINATION _ID_MSB R W 0x00 For a large common transport ...

Page 88: ... 0 CONF_OUT_PORT R W 0x00 Destination value through which all mes sages intended for CON_DESTID are sent 15 8 CONF_OUT_PORT_1 R W 0x00 Destination value through which all mes sages intended for CON_DESTID 1 are sent 23 16 CONF_OUT_PORT_2 R W 0x00 Destination value through which all mes sages intended for CON_DESTID 2 are sent 31 24 CONF_OUT_PORT_3 R W 0x00 Destination value through which all mes s...

Page 89: ...he multicast mask 3 1 Reserved 6 4 MASK_CMD R W 0b000 000 Write to verify 001 Add Port 010 Delete Port 100 Delete All Ports 101 Add all Ports 7 Reserved 15 8 EGRESS_PORT_NUMBER R W 0x00 Defines the port number which is modified queried by the MASK_CMD 31 16 MCAST_MASK R W 0x0000 Defines the multicast mask to be modified queried as determined by the MASK_CMD Table 10 19 MCAST_ASSOC_SEL_CSR 0x000084...

Page 90: ... write to ver ify command 0 no association 1 association present 4 1 Reserved 6 5 ASSOCIATION_COMMAND R W 0b00 Command when register is written 00 Write to Verify 01 Delete Association 11 Add association 7 TRANPORT_ASSOCIATION R W 0b0 0 small transport association 1 large transport association 31 8 Reserved Table 10 21 PORT_MAINT_BLOCK_HEAD 0x000100 Bit Field Name Type Reset Value Comment 15 0 EF_...

Page 91: ...se Address hex Associated Registers 0x000140 0x000144 0x000148 0x000158 0x00015C PORT_0_LINK_MAINT_REQ_CSR PORT_0_LINK_MAINT_RESP _CSr ORT_0_LOCAL_ACKID_CSR PORT_0_ERR_STAT_CSR PORT_0_CTRL_CSR 0x000160 0x00017C For PORT 1 0x000180 0x00019C For PORT 2 0x0001A0 0x0001BC For PORT 3 0x0001C0 0x0001DC For PORT 4 0x0001E0 0x0001FC For PORT 5 0x000200 0x00021C For PORT 6 0x000220 0x00023C For PORT 7 0x00...

Page 92: ...served 0b101 0b111 Reserved See RIO part 6 table 3 6 rev 1 3 31 3 Reserved Table 10 26 PORT_0_LINK_MAINT_RESP_CSR 0x000144 Bit Field Name Type Reset Value Comment 4 0 LINK_STATUS RO 0b00000 Link status field from the link response control symbol 9 5 ACKID_STATUS RO 0b00000 ackID status field from the link response control symbol 30 10 Reserved 31 RESPONSE_VALID RO 0b0 If the previous link request ...

Page 93: ...kets in order to manually implement error recovery 7 5 Reserved 12 8 OUTSTANDING_ACKID R W 0b00000 The output port unacknowledged ackID status The next acknowledge control symbol ackID field that indi cates the ackID value expected in the next received acknowledge con trol symbol 23 13 Reserved 28 24 INBOUND_ACKID R W 0b00000 Input port next expected ackID 30 29 Reserved 31 CLR_OUTSTANDING_ACKIDS ...

Page 94: ...OR RO 0b0 Input Error Port is stopped 9 INPUT_ERROR_ENCOUNTERED W1R 0b0 Input Error was encountered 10 INPUT_RETRY RO 0b0 Input Retry Port is stopped 15 11 Reserved 16 OUTPUT_ERROR RO 0b0 Output Error Port is stopped 17 OUTPUT_ERROR_ENCOUNTERED W1R 0b0 Output Error was encountered 18 OUTPUT_RETRY RO 0b0 Output Retry Port is stopped 19 OUTPUT_RETRIED RO 0b0 Output retried 20 OUTPUT_RETRY_ENCOUNTERE...

Page 95: ...T_ENABLE R W 0b0 Enable the Output port 23 PORT_DISABLE R W 0b0 Port Disable 26 24 PORT_WIDTH_OVERRIDE R W 0b000 000 no override 010 single lane port lane 0 011 single lane port lane 2 Others reserved 29 27 INIT_PORT_WIDTH RO 0b000 Initialized Port Width 000 single lane port lane 0 001 single lane port lane 2 010 4 Lane Port Others reserved 31 30 PORT_WIDTH RO 0b00 00 Single Lane Port 01 4 Lane Po...

Page 96: ...0 Access is for Global Route Table 0b00001 Access is for Port 0 Route Table 0b00010 Access is for Port 1 Route Table 0b00011 Access is for Port 2 Route Table 0b00100 Access is for Port 3 Route Table 0b00101 Access is for Port 4 Route Table 0b00110 Access is for Port 5 Route Table 0b00111 Access is for Port 6 Route Table 0b01000 Access is for Port 7 Route Table 0b01001 Access is for Port 8 Route Ta...

Page 97: ... 0x00 0xE10004 Port0 Device Route Table for Device ID 0x01 0xE103FC Port0 Device Route Table for Device ID 0xFF 0xE10400 Port0 Domain Route Table for Device ID 0x00 0xE10404 Port0 Domain Route Table for Device ID 0x01 0xE107FC Port0 Domain Route Table for Device ID 0xFF 0xE1F000 Port15 Device Route Table for Device ID 0x00 0xE1F004 Port15 Device Route Table for Device ID 0x01 0xE1F3FC Port15 Devic...

Page 98: ...00 0xE40398 Port 3 Trace Comparison Values and Masks Register 0xE40400 0xE40498 Port 4 Trace Comparison Values and Masks Register 0xE40500 0xE40598 Port 5 Trace Comparison Values and Masks Register 0xE40600 0xE40698 Port 6 Trace Comparison Values and Masks Register 0xE40700 0xE40798 Port 7 Trace Comparison Values and Masks Register 0xE40800 0xE40898 Port 8 Trace Comparison Values and Masks Registe...

Page 99: ... first 32 bits received in the packet Bit 31 will be compared to the first packet bit Bit 30 will be compared to the second packet bit Bit 0 will be compared to the 32nd packet bit Table 10 35 Port_0_Trace_Value_1_Block_1 0xE40004 Bit Field Name Type Reset Value Comment 31 0 COMPARISON_VALUE_1_BLOCK_1 R W 0x00000000 This value will be used for a bit by bit comparison against the first 32 bits rece...

Page 100: ...in the packet Bit 31 will be compared to the 65th packet bit Bit 30 will be compared to the 66th packet bit Bit 0 will be compared to the 96th packet bit Table 10 37 Port_0_Trace_Value_1_Block_3 0xE4000C Bit Field Name Type Reset Value Comment 31 0 COMPARISON_VALUE_1_BLOCK_3 R W 0x00000000 This value will be used for a bit by bit comparison against the first 32 bits received in the packet Bit 31 w...

Page 101: ... 32 bits received in the packet Bit 31 will be compared to the 129th packet bit Bit 30 will be compared to the 130th packet bit Bit 0 will be compared to the 160th packet bit Table 10 39 Port_0_Mask_Value_1_Block_0 0xE40014 Bit Field Name Type Reset Value Comment 31 0 MASK_VALUE_1_BLOCK_0 R W 0x00000000 This value will be used for a bit by bit mask against the corresponding comparison value Bit 31...

Page 102: ...lock_2 0xE4001C Bit Field Name Type Reset Value Comment 31 0 MASK_VALUE_1_BLOCK_2 R W 0x00000000 This value will be used for a bit by bit comparison against the first 32 bits received in the packet Bit 31 will be a mask for the 65th comparison bit Bit 30 will be a mask for the 66th comparison bit Bit 0 will be a mask for the 96th com parison bit Table 10 42 Port_0_Mask_Value_1_Block_3 0xE40020 Bit...

Page 103: ...e 130th comparison bit Bit 0 will be a mask for the 160th comparison bit Table 10 44 CPS_CONTROL 0xF2000C Bit Field Name Type Reset Value Comment 0 PORT_RESET_BEHAVIOR R W 0b0 Defines action upon reception of an sRIO reset control symbol 0 reset chip 1 reset port via which the symbol was received 4 1 TRACE_OUTPUT_PORT_ENABL E R W 0x0 Defines the output port via which traced packets are transmitted...

Page 104: ...fic and for trace match data 1 Trace Port will only be used for trace match data 19 16 Reserved 20 QUAD_OFF_0 R W 0b0 0 On 1 Off Quad sleep mode for power reduc tion 21 QUAD_OFF_1 R W 0b0 0 On 1 Off Quad sleep mode for power reduc tion 22 QUAD_OFF_2 R W 0b0 0 On 1 Off Quad sleep mode for power reduc tion 23 QUAD_OFF_3 R W 0b0 0 On 1 Off Quad sleep mode for power reduc tion 31 24 Reserved Table 10 ...

Page 105: ...is register is used for the user to define the domain this device belongs to Table 10 46 AUXPORT_ERR_REPORT_ENABLE 0xF20018 Bit Field Name Type Reset Value Comment 0 JTAG_ERR_REPORT_ENABLE R W 0b0 0 Disable JTAG Error Reporting 1 Enable JTAG Error Reporting 1 I2 C_ERR_REPORT_ENABLE R W 0b0 0 Disable I2 C Error Reporting 1 Enable I2 C Error Reporting 31 2 Reserved Table 10 47 MAINT_ERR_REPORT_ENABL...

Page 106: ...E_INFO register will apply to the Source_ID as well Table 10 49 RIO_PORT_WRITE_INFO 0xF20024 Bit Field Name Type Reset Value Comment 12 0 Reserved 14 13 PRIO R W 0b00 SRIO Priority to be used for port writes 15 LARGE_TRANS R W 0b0 0 use small device ID for port writes 1 use large device ID for port writes 23 16 PORT_WRITE_TARGET_DEVICE_ID R W 0x00 Defines the Port Write target device ID 31 24 DEVI...

Page 107: ...Y_IDENT_CAR 0xF2002C Bit Field Name Type Reset Value Comment 15 0 RIO_ASSY_VENDOR_IDENT R W 0x0000 This value will be assigned to the ASSY_VENDOR_IDENT field in the sRIO ASSY_IDENT_CAR 31 16 RIO_ASSY_IDENT R W 0x0000 This value will be assigned to the ASSY_IDENT field in the sRIO ASSY_IDENT_CAR Table 10 52 RIO_ASSY_INF_CAR 0xF20030 Bit Field Name Type Reset Value Comment 15 0 RIO_ASSY_REV R W 0x00...

Page 108: ...th EPROM read 1 Do not verify checksum with EPROM read 15 12 Reserved 22 16 CLK_DIVISOR R W 0x62 Value used to convert inter nal Sys_Clks to I2C clocks and derive internal timing parameters This value must be set such that the equation SYS_CLK CLK_DIVISOR 32 MHz The maximum value under stood by the device is 0x62 such that if this value is pro grammed to 0x62 the value of 0x62 will be used The min...

Page 109: ...er ation is complete and was suc cessful If successful this bit will stay high until the next sequence is initiated 22 I2C_READ_IN_PROGRESS RO 0b0 0 I2C read operation is not in progress 1 I2C read operation is in progress This bit will stay high as long as the sequence is in progress and then will go low upon its com pletion 23 I2C_CHKSUM_FAIL RO 0b0 A value of 1 indicates that the ckecksum verif...

Page 110: ... 1 indicates that an unexpected I2C start or stop was detected Reset on read 31 28 Reserved Base Address Hex Associated Registers 0xF30000 MULTICAST0 0xF30004 MULTICAST1 0xF30008 MULTICAST2 0xF3000C MULTICAST3 0xF30010 MULTICAST4 0xF30014 MULTICAST5 0xF30018 MULTICAST6 0xF3001C MULTICAST7 0xF30020 MULTICAST8 0xF30024 MULTICAST9 Table 10 55 I2C_MASTER_STAT_CTRL 0xF20054 Bit Field Name Type Reset Va...

Page 111: ...s not included in Multicast group 0 1 Port 6 is included in Multicast group 0 7 MCAST_PORT_7 R W 0b0 0 Port 7 is not included in Multicast group 0 1 Port 7 is included in Multicast group 0 8 MCAST_PORT_8 R W 0b0 0 Port 8 is not included in Multicast group 0 1 Port 8 is included in Multicast group 0 9 MCAST_PORT_9 R W 0b0 0 Port 9 is not included in Multicast group 0 1 Port 9 is included in Multica...

Page 112: ...sters 0xF40300 0xF4033C Switching Port 3 Registers 0xF40400 0xF4043C Switching Port 4 Registers 0xF40500 0xF4053C Switching Port 5 Registers 0xF40600 0xF4063C Switching Port 6 Registers 0xF40700 0xF4073C Switching Port 7 Registers 0xF40800 0xF4083C Switching Port 8 Registers 0xF40900 0xF4093C Switching Port 9 Registers 0xF40A00 0xF40A3C Switching Port 10 Registers 0xF40B00 0xF40B3C Switching Port ...

Page 113: ...b0010 RIO Priority Level 2 Input Buffer Size 23 20 Reserved 27 24 PRI_3_BUF_SIZE R W 0b0010 RIO Priority Level 3 Input Buffer Size 31 25 Reserved Table 10 60 PORT_0_OPS 0xF40004 Bit Field Name Type Reset Value Comment 0 RETRANSMISSION_MIMIC R W 0b0 0 Normal RIO defined retransmissions 1 retransmissions use new payload with old ackIDs 3 1 CRC_RETRANSMISSION_LIMIT R W 0b000 000 no retransmission lim...

Page 114: ...Trace Comparison Value 2 is enabled 11 ENABLE_TRACE_COMPARISON_3 R W 0b0 0 Trace Comparison Value 3 is disabled 1 Trace Comparison Value 3 is enabled 12 ENABLE_TRACE_COMPARISON_4 R W 0b0 0 Trace Comparison Value 4 is disabled 1 Trace Comparison Value 4 is enabled 13 ENABLE_FILTER_COMPARISON_1 R W 0b0 0b0 Filter not enabled 0b1 Filter enabled 14 ENABLE_FILTER_COMPARISON_2 R W 0b0 0b0 Filter not ena...

Page 115: ...ame Type Reset Value Comment 0 ERROR_REPORT_ENABLE R W 0b0 0 Disable Error Reporting from this port 1 Enable Error Reporting from this port 1 SWITCH_PORT_ERROR_REPORT_ENABLE R W 0b0 0 Disable error reporting from switch buffers 1 Enable error reporting from switch buffers 2 RETRY_ERROR_REPORT_ENABLE R W 0b0 0 Disable Retry Symbol Received Reporting from Port 1 Enable Retry Symbol Received Reportin...

Page 116: ... 1 Empty 4 PRI_0_OUTPUT_BUF_STATUS RO 0b0 0 Not Empty 1 Empty 5 PRI_1_OUTPUT_BUF_STATUS RO 0b0 0 Not Empty 1 Empty 6 PRI_2_OUTPUT_BUF_STATUS RO 0b0 0 Not Empty 1 Empty 7 PRI_3_OUTPUT_BUF_STATUS RO 0b0 0 Not Empty 1 Empty 8 PRI_0_OUTPUT_BUF_ALMOST_FULL_STATUS RO 0b0 0 Not Almost Full 1 Almost Full 9 PRI_1_OUTPUT_BUF_ALMOST_FULL_STATUS RO 0b0 0 Not Almost Full 1 Almost Full 10 PRI_2_OUTPUT_BUF_ALMOS...

Page 117: ...acknowl edgements issued by port 0 Table 10 65 PORT_0_SW_PKT_CNTR 0xF4001C Bit Field Name Type Reset Value Comment 31 0 SWITCH_PKT_COUNT RR 0x00000000 A saturating count of packets sent for transmission through the internal switch that originated from port 0 Table 10 66 PORT_0_TRACE_MATCH_CNTR_1 0xF40020 Bit Field Name Type Reset Value Comment 31 0 TRACE_COUNT_1 RR 0x00000000 A saturating count of...

Page 118: ...ts at port 0 that have met the defined trace criteria with comparison Value 3 Table 10 69 PORT_0_TRACE_MATCH_CNTR_4 0xF4002C Bit Field Name Type Reset Value Comment 31 0 TRACE_COUNT_4 RR 0x00000000 A saturating count of packets at port 0 that have met the defined trace criteria with comparison Value 4 Table 10 70 PORT_0_FILTER_MATCH_CNTR_1 0xF40030 Bit Field Name Type Reset Value Comment 31 0 FILT...

Page 119: ...nt 31 0 FILTER_COUNT_4 RR 0x00000000 A saturating count of packets that have met the defined filter criteria with comparison Value 4 Table 10 74 ERR_CAP_REG 0xFD0000 Bit Field Name Type Reset Value Comment 0 ALL_FLAG_STOP R W 0b0 0 Do not send maintenance packet even if all flags are set 1 When all error flags are asserted generate a maintenance packet And stop the error management function if COU...

Page 120: ... 6 bits 31 14 Reserved Base Address Hex Associated Registers 0xFD0008 SPECIAL_ERR_REG_0 0xFD000C SPECIAL_ERR_REG_1 0xFD0010 SPECIAL_ERR_REG_2 0xFD0014 SPECIAL_ERR_REG_3 0xFD0018 SPECIAL_ERR_REG_4 0xFD001C SPECIAL_ERR_REG_5 0xFD0020 SPECIAL_ERR_REG_6 0xFD0024 SPECIAL_ERR_REG_7 Table 10 77 SPECIAL_ERR_0 0xFD0008 Bit Field Name Type Reset Value Comment 3 0 ERROR_NUMBER R W 0b0000 Error code 7 4 ERROR...

Page 121: ...0 Enable flagging the error 19 COUNT_ENABLE R W 0b0 Enable counting the error 20 ERROR_NUMBER_MASK R W 0b0 0 compare the error number 1 do not compare the error number 21 ERROR_GROUP_MASK R W 0b0 0 compare the error group 1 do not compare the error group 22 ERROR_SOURCE_MASK R W 0b0 0 compare the error source 1 do not compare the error source 31 23 Reserved Table 10 77 SPECIAL_ERR_0 0xFD0008 Bit F...

Page 122: ...indicate and error applies to Special error register 2 3 FLAG_ERROR_3 RR 0b0 Assert this field to indicate and error applies to Special error register 3 4 FLAG_ERROR_4 RR 0b0 Assert this field to indicate and error applies to Special error register 4 5 FLAG_ERROR_5 RR 0b0 Assert this field to indicate and error applies to Special error register 5 6 FLAG_ERROR_6 RR 0b0 Assert this field to indicate...

Page 123: ... 0b0 Resets the flag register 2 COUNT_RESET R W 0b0 Resets the error count regis ter 3 ERROR_FIFO_RESET R W 0b0 Reset the error FIFO 4 MAINTENANCE_PACKET_DISABLE R W 0b0 0 generation of the main tenance packet is enabled 1 generation of the main tenance packet is disabled 5 STOP R W 0b0 Stops the error manage ment function Setting this bit to 1 will disable all port writes including those that res...

Page 124: ...L QUAD_3_ERROR_REPORT_EN 0xFFF000 Broadcast To All Quads Register Table 10 82 QUAD_0_CTRL 0xFF0000 Bit Field Name Type Reset Value Comment 1 0 SPEEDSEL R W 0b00 Port Speed Selection Default is set by external pins 00 1 25 Gbps 01 2 5 Gbps 10 3 125 Gbps 4 2 TCOEFF R W 0b000 Transmitter Pre emphasis 000 0 001 6 5 010 13 011 19 5 100 26 101 32 5 110 39 111 45 5 5 STD_ENH_SEL R W 0b1 0 standard 1 enha...

Page 125: ...ate Port Speed Selection for Lanes 2 and 3 Only active if 16 1 00 1 25 Gbps 01 2 5 Gbps 10 3 125 Gbps Default is set by external pins same as con figuration for Lanes 1 and 2 21 19 LANE23_TCOEFF R W 0b000 Separate Transmitter Pre emphasis for Lanes 2 and 3 Only active if 16 1 000 0 001 6 5 010 13 011 19 5 100 26 101 32 5 110 39 111 45 5 22 LANE23_FORCE_REINIT R W 0b0 Force init on Lanes 2 and 3 On...

Page 126: ... Enables error reporting on a per quad basis 0 disable 1 enable 31 1 Reserved Table 10 84 QUAD_CTRL_BROADCAST 0xFFF000 Bit Field Name Type Reset Value Comment 1 0 SPEEDSEL W 0b00 Port Speed Selection default is set by external pins 00 1 25 Gbps 01 2 5 Gbps 10 3 125 Gbps 4 2 TCOEFF W 0b000 Transmitter Pre emphasis 000 0 001 6 5 010 13 011 19 5 100 26 101 32 5 110 39 111 45 5 5 STD_ENH_SEL W 0b1 0 s...

Page 127: ...Port Speed Selection for Lanes 2 and 3 Only active if 16 1 00 1 25 Gbps 01 2 5 Gbps 10 3 125 Gbps Default is set by external pins same as configuration for Lanes 1 and 2 21 19 LANE23_TCOEFF R W 0b000 Separate Transmitter Pre emphasis for Lanes 2 and 3 Only active if 16 1 000 0 001 6 5 010 13 011 19 5 100 26 101 32 5 110 39 111 45 5 22 LANE23_FORCE_REINIT R W 0b0 Force init on Lanes 2 and 3 Only ac...

Page 128: ... 1x 4x LP Serial Specification Rev 1 3 5 RapidIO Interconnect Specification Part 7 System and Device Inter operability Specification Rev 1 3 6 RapidIO Interconnect Specification Part 9 Flow Control Logic Layer Extensions Specification Rev 1 3 7 RapidIO Interconnect Specification Part 11 Multicast Extensions Specification Rev 1 3 8 RapidIO Interconnect Specification Annex I Software System Bring Up...

Page 129: ...ied including but not limited to the suitability of IDT s products for any particular purpose an implied warranty of merchantability or non infringement of the intellectual property rights of others This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties IDT s products are not intended for use in life support systems...

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