IDT JTAG & Boundary Scan
Revision 1.5
Integrated Device Technology, Inc.
CPS-16/12/8 User Manual
6 - 2
July 10, 2012
6.3 DEVICE ID REGISTER
The JTAG Device ID register length is 32 bits wide. The Capture Data Register value is the Device ID.
The JTAG Device ID register is mapped to the DEV_IDENT field in the DEV_IDENT_CAR as defined in the
“Registers” section of this document. The device provides no correlation between the value in this register
and the device’s I
2
C address. There is no provision to read the I
2
C address from the TAP port.
The 11 bit JTAG Vendor ID is 0xB3 where the MSB = 1 (the code itself uses an ODD parity bit in the 8th bit.
Per the JTAG specification, the first 7 bits of the Vendor ID will be the first 7 bits of the EIA/JEP106 code
“discarding the parity bit.” Thus, the JTAG IDCODE read from the TAP port will match 0x33, and to 0xB3.
6.4 INITIALIZATION AND RESET
At Power-Up, TRST must be asserted LOW to bring the TAP controller up in a known, reset state. Per
IEEE 1149.1 specification, the user can alternatively hold the TMS pin high while clocking TCK five times
(minimum) to reset the controller. To deactivate JTAG, TRST is tied low so that the TAP controller remains
in a known state at all times. All of the other JTAG input pins are internally biased in such a way that by
leaving them unconnected they are automatically disabled. Note that JTAG inputs are OK to float because
they have leakers (as required by IEEE 1149.1 specification).
6.5 CONFIGURATION REGISTER ACCESS
The same JTAG instruction is used for both writes and reads of the Configuration Register space. Bit zero
of the TDI data stream is used to define whether the command is a write or a read.
0xE
Die_Signature
Dumps fab information including die location, version, and
wafer number
0xF
Bypass
Implemented per IEEE 1149.1-2001
Table 6.2 Configuration Registers
Bits
Field Name
Size
Description
[0]
jtag_config_wr_n
1
1 - read configuration register
0 - write configuration register
[22:1]
jtag_config_addr
22
Starting address of the memory mapped configuration
register
[54:23]
jtag_config_data
32
Reads: Data shifted out (one 32-bit word per read) is
read from the configuration register at address
jtag_config_addr.
Writes: Data shifted in (one 32-bit word per write) is
written to the configuration register at address
jtag_config_addr.
Table 6.1 Test Instructions
IR Code [3:0]
Instruction
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