IDT Reset & Initialization
Revision 1.5
Integrated Device Technology, Inc.
CPS-16/12/8 User Manual
9 - 2
July 10, 2012
The device provides two external pins, (SPD0 and SPD1) which determines the initial (default) port speed.
These pins support the configurations defined below:
9.2 INITIALIZATION STEPS
The CPS supports the following initialization steps.
The reset signal need not be held low for more than 5 REF-CLK cycles.
1) Initialize RIO PHY and ports.
a. The default setting for PHYs and links are set at this point.
b. PHYs start communicating with other neighbor devices.
2) Initialize the memory, and registers
a. This includes setting registers and memories to their default values
9.3 INITIALIZATION OF RIO PORTS
The CPS device supports the initialization of RIO Ports as defined in Physical Layer Specification section
rev 1.3. It provides registers which allow the user to define port configuration, speed, and AC Timing Speci-
fication (long run/short run). These registers are programmable through the I
2
C or JTAG interfaces during
system initialization as well.
9.4 RIO SYSTEM BRING UP
The device supports the “system bring up” requirements defined in the RapidIO System Interconnect Spec-
ification Annex 1 -- Software and System Bringup Specification.
9.5 SERDES INITIALIZATION
SERDES Initialization for the CPS is defined in Chapter 6 of the RIO specification. Upon reset the TX
drivers will drive a logic “0” out onto the serial port. After reset this logical “0” is held for a predetermined
number of clock cycles. This number of clock cycles are register controlled. These register contents are
compared to an 8-bit counter. Once they match, the TX drivers are released and transmission of the idle
sequence begins. Once the lanes are synchronized, in 1X mode, or aligned in 4X mode, port_initialized (as
defined in RIO Chapter 6) will be driven to a logical “1”. This is the indicator to the PHY that the link is ready.
Table 9.2 Default Speed Settings with SPD0 and SPD1
SPD1/SPD0 States
Port Speed
00
1.25 Gbits/sec
01
2.5 Gbits/sec
10
3.125 Gigabits/sec
11
Reserved