IDT Programming the Device
Revision 1.5
Integrated Device Technology, Inc.
CPS-16/12/8 User Manual
8 - 11
July 10, 2012
to favorable values (typically zero) before the clocks are gated off. In this way, when the register
clocks are restored, there will not be any stale values in the registers that could cause the port logic
to behave in expected ways.
19. The output-retry state machine and output-error state machine are returned to their initial states,
regardless of what the state was at the time the reset was received (including the stopped states
and the fatal error state).
20. When the port does not receive a link-response control symbol following the transmission of a link-
request/input-status control symbol, a link-response timeout event occurs. The port will then
retransmit the link-request/input-status symbol which may again timeout. The CPS parts allow this
process to iterate repeatedly up to 16 timeouts of the link-response before declaring a fatal-error
condition. There is a counter associated with counting how many times the link-request/input-status
symbol has been transmitted in this loop. That counter is cleared by a local soft reset event.
21. Most of the sRIO-defined port-level CSRs are not modified or cleared by a local soft reset event. The
exceptions in the CPS design are in the PortN_error_and_status CSR and include the port_uninit
bit which is set high and the following fields which are cleared to zero: port_ok, port_error,
input_error, input_error_encountered, input_retry, output_error, output_error_encountered,
output_retry, output_retried, and output_retry_encountered.
22. The 1x/2x/Nx initialization state machine is returned to the initial state, regardless of what the state
was at the time the reset was received. Since this involves returning to the SILENT state, the traffic
on all lanes will be disabled which will force loss of link with the lane partner. This will cause link re-
negotiation to occur in the same way as if the force_reinit function had been invoked.
8.3.3 Reset Configuration
After resetting the CPS, the ports are set to their default configuration, with the port speed dictated by the
speed pins (refer to the Reset & Initialization chapter). Since the serial RapidIO
standard does not dictate a
power-up speed setting, subsequent in-band sRIO programming requires the system designer ensure there
is a path of connectivity from the host processor to the CPS via sRIO ports of compatible speed and config-
uration.
If CPS device boots from external EEPROM, the setting dependents on the setting image. The booting
status is reflected in the I2C master status register.
8.3.4 Port Configuration
The next step after resetting the CPS to its default state is to configure the physical ports. As usual, this can
be accomplished by the I
2
C or JTAG ports, or by in-band sRIO maintenance packets.
8.3.5 Error Report Enables
To detect errors as early as possible (even those during the initial programming sequence), the error
reporting features of the CPS should be taken advantage of in this early stage of configuring the CPS.
Errors are reported from any of several major architectural blocks aboard the CPS. Since the error reporting
field defaults to OFF at reset, it is recommended that the user enable reporting for all architectural blocks.
For early debug, the Err_Report_Enable bit should be set for each of the following:
Config_mod_err_report_enable
I
2
C_err_report_enable
JTAG_err_report_enable
Quad_err_report_enable
Errors will then be reported by all enabled blocks to the Error Management block. Refer to the “Error
Management” chapter for full detail on the error handling features, and a full listing of error codes that is
reported.
To better isolate a given type of fail, or as the system is fully debugged, the user might choose to throttle
back the number of reporting blocks.
