IDT 89HPES16T4AG2, User Manual

Page: 89 / 165

IDT Configuration Registers
PES16T4AG2 User Manual 8 - 7 May 23, 2013
Notes
0x00C Byte Px_CLS CLS - Cache Line Size Register (0x00C) on page 8-13
0x00D Byte Px_PLTIMER PLTIMER - Primary Latency Timer (0x00D) on page 8-13
0x00E Byte Px_HDR HDR - Header Type Register (0x00E) on page 8-13
0x00F Byte Px_BIST BIST - Built-in Self Test Register (0x00F) on page 8-13
0x010 DWord Px_BAR0 BAR0 - Base Address Register 0 (0x010) on page 8-13
0x014 DWord Px_BAR1 BAR1 - Base Address Register 1 (0x014) on page 8-14
0x018 Byte Px_PBUSN PBUSN - Primary Bus Number Register (0x018) on page 8-14
0x019 Byte Px_SBUSN SBUSN - Secondary Bus Number Register (0x019) on page 8-14
0x01A Byte Px_SUBUSN SUBUSN - Subordinate Bus Number Register (0x01A) on page 8-14
0x01B Byte Px_SLTIMER SLTIMER - Secondary Latency Timer Register (0x01B) on page 8-14
0x01C Byte Px_IOBASE IOBASE - I/O Base Register (0x01C) on page 8-15
0x01D Byte Px_IOLIMIT IOLIMIT - I/O Limit Register (0x01D) on page 8-15
0x01E Word Px_SECSTS SECSTS - Secondary Status Register (0x01E) on page 8-15
0x020 Word Px_MBASE MBASE - Memory Base Register (0x020) on page 8-16
0x022 Word Px_MLIMIT MLIMIT - Memory Limit Register (0x022) on page 8-16
0x024 Word Px_PMBASE PMBASE - Prefetchable Memory Base Register (0x024) on page 8-
16
0x026 Word Px_PMLIMIT PMLIMIT - Prefetchable Memory Limit Register (0x026) on page 8-17
0x028 DWord Px_PMBASEU PMBASEU - Prefetchable Memory Base Upper Register (0x028) on
page 8-17
0x02C DWord Px_PMLIMITU PMLIMITU - Prefetchable Memory Limit Upper Register (0x02C) on
page 8-17
0x030 Word Px_IOBASEU IOBASEU - I/O Base Upper Register (0x030) on page 8-17
0x032 Word Px_IOLIMITU IOLIMITU - I/O Limit Upper Register (0x032) on page 8-18
0x034 Byte Px_CAPPTR CAPPTR - Capabilities Pointer Register (0x034) on page 8-18
0x038 DWord Px_EROMBASE EROMBASE - Expansion ROM Base Address Register (0x038) on
page 8-18
0x03C Byte Px_INTRLINE INTRLINE - Interrupt Line Register (0x03C) on page 8-18
0x03D Byte Px_INTRPIN INTRPIN - Interrupt PIN Register (0x03D) on page 8-19
0x03E Word Px_BCTL BCTL - Bridge Control Register (0x03E) on page 8-19
0x040 DWord Px_PCIECAP PCIECAP - PCI Express Capability (0x040) on page 8-20
0x044 DWord Px_PCIEDCAP PCIEDCAP - PCI Express Device Capabilities (0x044) on page 8-21
0x048 Word Px_PCIEDCTL PCIEDCTL - PCI Express Device Control (0x048) on page 8-22
0x04A Word Px_PCIEDSTS PCIEDSTS - PCI Express Device Status (0x04A) on page 8-23
0x04C DWord Px_PCIELCAP PCIELCAP - PCI Express Link Capabilities (0x04C) on page 8-24
0x050 Word Px_PCIELCTL PCIELCTL - PCI Express Link Control (0x050) on page 8-25
0x052 Word Px_PCIELSTS PCIELSTS - PCI Express Link Status (0x052) on page 8-27
Cfg.
Offset
Size
Register
Mnemonic
Register Definition
Table 8.3 Downstream Ports 1 through 5 Configuration Space Registers (Part 2 of 5)