IDT 89HPES16T4AG2, User Manual

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IDT Configuration Registers
PES16T4AG2 User Manual 8 - 21 May 23, 2013
Notes PCIEDCAP - PCI Express Device Capabilities (0x044)
Bit
Field
Field
Name
Type
Default
Value
Description
2:0 MPAYLOAD RWL HWINIT Maximum Payload Size Supported . This field indicates the
maximum payload size that the device can support for TLPs.
For all bond options the default value is 0x4 which corresponds to
2048 bytes.
4:3 PFS RO 0x0 Phantom Functions Supported . This field indicates the support
for unclaimed function number to extend the number of outstand-
ing transactions allowed by logically combining unclaimed func-
tion numbers. The value is hardwired to 0x0 to indicate that no
function number bits are used for phantom functions.
5 ETAG RWL 0x1 Extended Tag Field Support. This field indicates the maximum
supported size of the Tag field as a requester.
8:6 E0AL RO 0x0 Endpoint L0s Acceptable Latency. This field indicates the
acceptable total latency that an endpoint can withstand due to
transition from the L0s state to the L0 state. The value is hard-
wired to 0x0 as this field does not apply to a switch.
11:9 E1AL RO 0x0 Endpoint L1 Acceptable Latency. This field indicates the
acceptable total latency that an endpoint can withstand due to
transition from the L1 state to the L0 state. The value is hardwired
to 0x0 as this field does not apply to a switch.
12 ABP RO 0x0 Attention Button Present. In PCIe base 1.0a when set, this bit
indicates that an Attention Button is implemented on the card/
module.
The value of this field is undefined in PCIe base 1.1
13 AIP RO 0x0 Attention Indicator Present. In PCIe base 1.0a when set, this
bit indicates that an Attention Indicator is implemented on the
card/module.
The value of this field is undefined in PCIe base 1.1
14 PIP RO 0x0 Power Indicator Present. In PCIe base 1.0a when set, this bit
indicates that a Power Indicator is implemented on the card/mod-
ule.
The value of this field is undefined in PCIe base 1.1
15 RBERR RO 0x1 Role Based Error Reporting. This bit is set to indicate that the
PES16T4AG2 supports error reporting as defined in the PCIe
base 1.1 specification.
17:16 Reserved RO 0x0 Reserved.
25:18 CSPLV RO 0x0 Captured Slot Power Limit Value. This field in combination with
the Slot Power Limit Scale value, specifies the upper limit on
power supplied by the slot. Power limit (in Watts) calculated by
multiplying the value in this field by the value in the Slot Power
Limit Scale field.
The value of this field is set by a Set_Slot_Power_Limit Message
and is only applicable for the upstream port. This field is always
zero in downstream ports.