IDT 89HPES16T4AG2, User Manual

Page: 87 / 165

IDT Configuration Registers
PES16T4AG2 User Manual 8 - 5 May 23, 2013
Notes
0x188 Dword P0_SNUMUDW SNUMUDW - Serial Number Upper Doubleword (0x188) on page 8-
48
0x200 DWord P0_PCIEVCECAP PCIEVCECAP - PCI Express VC Enhanced Capability Header
(0x200) on page 8-49
0x204 DWord P0_PVCCAP1 PVCCAP1- Port VC Capability 1 (0x204) on page 8-49
0x208 DWord P0_PVCCAP2 PVCCAP2- Port VC Capability 2 (0x208) on page 8-50
0x20C Word P0_PVCCTL PVCCTL - Port VC Control (0x20C) on page 8-50
0x20E Word P0_PVCSTS PVCSTS - Port VC Status (0x20E) on page 8-50
0x210 DWord P0_VCR0CAP VCR0CAP- VC Resource 0 Capability (0x210) on page 8-51
0x214 DWord P0_VCR0CTL VCR0CTL- VC Resource 0 Control (0x214) on page 8-51
0x218 DWord P0_VCR0STS VCR0STS - VC Resource 0 Status (0x218) on page 8-52
0x220 DWord P0_VCR0TBL0 VCR0TBL0 - VC Resource 0 Arbitration Table Entry 0 (0x220) on
page 8-53
0x224 DWord P0_VCR0TBL1 VCR0TBL1 - VC Resource 0 Arbitration Table Entry 1 (0x224) on
page 8-53
0x228 DWord P0_VCR0TBL2 VCR0TBL2 - VC Resource 0 Arbitration Table Entry 2 (0x228) on
page 8-54
0x22C DWord P0_VCR0TBL3 VCR0TBL3 - VC Resource 0 Arbitration Table Entry 3 (0x22C) on
page 8-54
0x280 Dword P0_PWRBCAP PWRBCAP - Power Budgeting Capabilities (0x280) on page 8-55
0x284 Dword P0_PWRBDSEL PWRBDSEL - Power Budgeting Data Select (0x284) on page 8-55
0x288 Dword P0_PWRBD PWRBD - Power Budgeting Data (0x288) on page 8-56
0x28C Dword P0_PWRBPBC PWRBPBC - Power Budgeting Power Budget Capability (0x28C) on
page 8-56
0x300 Dword P0_PWRBDV0 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C)
on page 8-56
0x304 Dword P0_PWRBDV1 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C)
on page 8-56
0x308 Dword P0_PWRBDV2 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C)
on page 8-56
0x30C Dword P0_PWRBDV3 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C)
on page 8-56
0x310 Dword P0_PWRBDV4 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C)
on page 8-56
0x314 Dword P0_PWRBDV5 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C)
on page 8-56
0x318 Dword P0_PWRBDV6 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C)
on page 8-56
0x31C Dword P0_PWRBDV7 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C)
on page 8-56
0x400 DWord SWSTS SWSTS - Switch Status (0x400) on page 8-56
Cfg.
Offset
Size
Register
Mnemonic
Register Definition
Table 8.2 Upstream Port 0 Configuration Space Registers (Part 4 of 5)