IDT 89HPES16T4AG2, User Manual

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IDT PES16T4AG2 Device Overview
PES16T4AG2 User Manual 1 - 2 May 23, 2013

Testability and Debug Features
– Built in Pseudo-Random Bit Stream (PRBS) generator
– Numerous SerDes test modes
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters

Seven General Purpose Input/Output Pins
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions

Packaged in a 19mm x 19mm, 324-ball Flip Chip BGA with 1mm ball spacing
Figure 1.1 PES16T4AG2 Architectural Block Diagram
TDM Demux
D-Bus
U-Bus
ESP
&
Arb
ESP
&
Arb
ESP
&
Arb
ESP
&
Arb
Route Map
Table
Ingress
Processor
TLP
Checker
Egress
Processor
Completion
Processor
Message
Processor
TLP
Generator
Hot-Plug
Controller
Application Layer
Data Link Layer
Physical Layer & SerDes Mux/Demux
SerDes SerDes
Port 0 Port 1 Port 2 Port 3
Switch Core
GPIO
Controller
Master
SMBus
Interface
Reset
Controller
Slave
SMBus
Interface
Output &
Replay Buffer
TDM Demux
Route Map
Table
Ingress
Processor
TLP
Checker
Egress
Processor
Completion
Processor
Message
Processor
TLP
Generator
Hot-Plug
Controller
Application Layer
Data Link Layer
Physical Layer & SerDes Mux/Demux
SerDes SerDes
Output &
Replay Buffer
Input
Frame
Buffer
Input
Frame
Buffer
Input
Frame
Buffer
Input
Frame
Buffer
D-Bus
Arbiter
U-Bus
Arbiter
Bus Decoupler
Queue