IDT 89HPES16T4AG2, User Manual

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IDT SMBus Interfaces
PES16T4AG2 User Manual 5 - 14 May 23, 2013
Notes
Initialization
Slave SMBus initialization occurs during a fundamental reset (see section Fundamental Reset on page
2-2). During the fundamental reset initialization sequence, the slave SMBus address is initialized. The
address specified by the SSMBADDR[5,3:1] signals is hardwired to 0x77.
SMBus Transactions
The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master
(see the SMBus 2.0 specification for a detailed description of these transactions):
– Byte and Word Write/Read
– Block Write/Read
Initiation of any SMBus transaction other than those listed above to the slave SMBus interface produces
undefined results. Associated with each of the above transactions is a command code. The command code
format for operations supported by the slave SMBus interface is shown in Figure 5.5 and described in Table
5.10.
Figure 5.5 Slave SMBus Command Code Format
The FUNCTION field in the command code indicates if the SMBus operation is a CSR register read/
write or a serial EEPROM read/write operation. Since the format of these transactions is different. They will
be described individually in the following sections. If a command is issued while one is already in progress
or if the slave is unable to supply data associated with a command, the command is NACKed. This indi-
cates to the master that the transaction should be retried.
Bit
Field
Name Description
0 END End of transaction indicator. Setting both START and END signifies a
single transaction sequence
0 - Current transaction is not the last read or write sequence.
1 - Current transaction is the last read or write sequence.
1 START Start of transaction indicator. Setting both START and END signifies a
single transaction sequence
0 - Current transaction is not the first of a read or write sequence.
1 - Current transaction is the first of a read or write sequence.
4:2 FUNC-
TION
This field encodes the type of SMBus operation.
0 - CSR register read or write operation
1 - Serial EEPROM read or write operation
2 through 7 - Reserved
6:5 SIZE This field encodes the data size of the SMBus transaction.
0 - Byte
1 - Word
2 - Block
3 - Reserved
7 PEC This bit controls whether packet error checking is enabled for the cur-
rent SMBus transaction.
0 - Packet error checking disabled for the current SMBus transaction.
1 - Packet error checking enabled for the current SMBus transaction.
Table 5.10 Slave SMBus Command Code Fields
Bit
6
Bit
7
Bit
0
Bit
1
Bit
2
Bit
3
Bit
4
Bit
5
END START FUNCTION SIZE PEC