IDT 89HPES16T4AG2, User Manual

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IDT Configuration Registers
PES16T4AG2 User Manual 8 - 63 May 23, 2013
Notes
SMBUSCTL - SMBus Control (0x428)
EEPROMINTF - Serial EEPROM Interface (0x42C)
26 LAERR RW1C 0x0 Lost Arbitration Error. When the master SMBus interface loses
arbitration for the SMBus, it automatically re-arbitrates for the
SMBus. If the master SMBus interface loses 16 consecutive arbi-
tration attempts, then the transaction is aborted and this bit is set.
27 OTHERERR RW1C 0x0 Other Error. This bit is set if a misplaced START or STOP condi-
tion is detected by the master SMBus interface.
28 ICSERR RW1C 0x0 Initialization Checksum Error. This bit is set if an invalid check-
sum is computed during Serial EEPROM initialization or when a
configuration done command is not found in the serial EEPROM.
29 URIA RW1C 0x0 Unmapped Register Initialization Attempt. This bit is set if an
attempt is made to initialize via serial EEPROM a register that is
not defined in the corresponding PCI configuration space.
31:30 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
15:0 MSMBCP RW HWINIT
Sticky
Master SMBus Clock Prescalar. This field contains a clock
prescalar value used during master SMBus transactions. The
prescalar clock period is equal to 32 ns multiplied by the value in
this field. When the field is cleared to zero or one, the clock is
stopped.
The value of this field is set to 0x0053
1
because the master
SMBus clock operates at 400 KHz.
1.
The MSMBCLK low minimum pulse width is equal to half the period programmed in this field. The value of 0x53, which corre-
sponds to ~373 KHz, allows the min low pulse width to be satisfied. In systems where this timing parameter is not critical, the op-
erating frequency may be increased.
16 MSMBIOM RW 0x0
Sticky
Master SMBus Ignore Other Masters. When this bit is set, the
master SMBus proceeds with transactions regardless of whether
it won or lost arbitration.
17 ICHECKSUM RW 0x0
Sticky
Ignore Checksum Errors. When this bit is set, serial EEPROM
initialization checksum errors are ignored (i.e., the checksum
always passes).
21:18 Reserved RO 0x0 Reserved field.
22 SMBDTO RW 0x0 SMBus Disable Time-out. When this bit is set, SMBus time-outs
are disabled on the master and slave SMBuses.
31:23 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
15:0 ADDR RW 0x0 EEPROM Address. This field contains the byte address in the
Serial EEPROM to be read or written.
Bit
Field
Field
Name
Type
Default
Value
Description