IDT 89HPES16T4AG2, User Manual

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IDT Configuration Registers
PES16T4AG2 User Manual 8 - 43 May 23, 2013
Notes
18 MAL-
FORMED
RW 0x0
Sticky
Malformed TLP Mask. When this bit is set, the corresponding bit
in the AERUES register is masked. When a bit is masked in the
AERUES register, the corresponding event is not logged in the
advanced capability structure, the First Error Pointer field
(FEPTR) in the AERCTL register is not updated, and an error is
not reported to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
19 ECRC RW 0x0
Sticky
ECRC Mask. When this bit is set, the corresponding bit in the
AERUES register is masked. When a bit is masked in the
AERUES register, the corresponding event is not logged in the
advanced capability structure, the First Error Pointer field
(FEPTR) in the AERCTL register is not updated, and an error is
not reported to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
20 UR RW 0x0
Sticky
UR Mask. When this bit is set, the corresponding bit in the
AERUES register is masked. When a bit is masked in the
AERUES register, the corresponding event is not logged in the
advanced capability structure, the First Error Pointer field
(FEPTR) in the AERCTL register is not updated, and an error is
not reported to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
21 ACSV RW 0x0
Sticky
ACS Violation Mask. When this bit is set, the corresponding bit
in the AERUES register is masked. When a bit is masked in the
AERUES register, the corresponding event is not logged in the
advanced capability structure, the First Error Pointer field
(FEPTR) in the AERCTL register is not updated, and an error is
not reported to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
30:22 Reserved RO 0x0 Reserved field.
31 DBE RW 0x0
Sticky
Double Bit Error Mask. When this bit is set and the Double Bit
Error AER Reporting Enable (DBEAEREN) bit is set in the Mem-
ory Error Control (MECTL) register, the corresponding bit in the
AERUES register is masked.
When a bit is masked in the AERUES register, the corresponding
event is not logged in the advanced capability structure, the First
Error Pointer field (FEPTR) in the AERCTL register is not
updated, and an error is not reported to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
When the DBEAEREN bit is cleared, this field is read-only zero.
Bit
Field
Field
Name
Type
Default
Value
Description