IDT 89HPES16T4AG2, User Manual

Page: 80 / 165

IDT Hot-Plug and Hot-Swap
PES16T4AG2 User Manual 7 - 4 May 23, 2013
Notes ated Retention Latch Sensor State (MRLSS) status is always reported as closed (i.e., zero). When the
RMRLWEMIL bit is cleared, the EIS bit state in the PCIESSTS register always returns the value of the
corresponding PxILOCKP I/O expander signal output.
When the MRL Automatic Power Off (MRLPWROFF) bit is set in the HPCFGCTL register and the
Manual Retention Latch Present (MRLP) bit is set in the PCI Express Slot Capability (PCIESCAP) register,
power to the slot is automatically turned off when the MRL sensor indicates that the MRL is open. This
occurs regardless of the state of the Power Controller Control (PCC) bit in the PCI Express Slot Control
(PCIESCTL) register.
The state of a port’s Power Fault (PxPFN) input is not latched by the PES16T4AG2. For proper opera-
tion the system designer should ensure that once the PxPFN signal is asserted, it remains asserted until
the power enable (PxPEP) signal is toggled. This is required adapter behavior for the PCI Express Express-
Module form factor.
Downstream port reset outputs are described in section Downstream Port Reset Outputs on page 2-7.
The default value of hot-plug registers following a hot or fundamental reset may be configured via serial
EEPROM initialization. Since hot-plug I/O expander initialization occurs after serial EEPROM initialization,
the Command Completed (CC) bit is not set in the PCI Express Slot Status (PCIESSTS) register as a result
of serial EEPROM initialization. Following a Hot-Reset to the Entire Device (see section Hot Reset on page
2-5) or an Upstream Secondary Bus Hot-Reset (see section Upstream Secondary Bus Reset on page 2-6),
each downstream port’s PHY will transition the links to the Hot-Reset state and subsequently re-train the
link starting from the Detect state. When this occurs, the Hot-Plug controller for the port does not set the
Presence Detect Changed (PDC) bit in the PCIESSTS register.
Hot-Plug I/O Expander
The PES16T4AG2 utilizes external SMBus/I
2
C-bus I/O expanders connected to the master SMBus
interface for hot-plug related signals associated with downstream ports. See section I/O Expanders on page
5-7 for details on the operation of the I/O expanders and for the mapping of downstream hot-plug signals to
I/O expander inputs and outputs.
Hot-Plug Interrupts and Wake-up
The hot-plug controller associated with a downstream slot may generate an interrupt or wakeup event.
Hot-plug interrupts are only generated when the Hot Plug Interrupt Enable (HPIE) bit is set in the corre-
sponding port’s PCI Express Slot Control (PCIESCTL) register. The following bits, when set in the PCI
Express Slot Status (PCIESSTS) register, generate an interrupt if not masked by the corresponding bit in
the PCI Express Slot Control (PCIESCTL) register or by the HPIE bit:
– Attention Button Pressed (ABP)
– Power Fault Detected (PFD)
– MRL Sensor Changed (MRLSC)
– Presence Detected Changed (PDC)
– Command Completed (CC).
When an unmasked hot-plug interrupt is generated, the action taken is determined by the MSI Enable
(EN) bit in the MSI Capability (MSICAP) register and the Interrupt Disable (INTXD) bit in the PCI Command
(PCICMD) register. When the downstream port or the entire switch is in a D3
hot
state, the hot-plug controller
generates a wakeup event using a PM_PME message instead of an interrupt if the event interrupt is not
masked in the slot control (PCIESCTL) register and hot-plug interrupts are disabled by the HPIE bit. If the
event interrupt is not masked and hot-plug interrupts are enabled, both a PM_PME and an interrupt are
generated. If the event interrupt is masked, then neither a PM_PME nor an interrupt is generated. Note that
a command completed (CC bit) interrupt will not generate a wakeup event.