IDT 89HPES16T4AG2, User Manual

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IDT Configuration Registers
PES16T4AG2 User Manual 8 - 11 May 23, 2013
Notes
PCISTS - PCI Status Register (0x006)
1 MAE RW 0x0 Memory Access Enable. When this bit is cleared, the bridge
does not respond to memory and prefetchable memory space
access from the primary bus specified by MBASE, MLIMIT,
PMBASE and PMLIMIT.
0x0 - (disable) Disable memory space.
0x1 - (enable) Enable memory space.
2 BME RW 0x0 Bus Master Enable. When this bit is cleared, the bridge does not
issue requests (e.g., memory, I/O and MSIs since they are in-
band writes) on behalf of subordinate devices and handles these
as Unsupported Requests (UR). Additionally, the bridge handles
non-posted transactions in the upstream direction with a Unsup-
ported Request (UR) completion. This bit does not affect comple-
tions in either direction or the forwarding of non memory or I/O
requests.
0x0 - (disable) Disable request forwarding.
0x1 - (enable) Enable request forwarding.
3 SSE RO 0x0 Special Cycle Enable. Not applicable.
4 MWI RO 0x0 Memory Write Invalidate. Not applicable.
5 VGAS RO 0x0 VGA Palette Snoop . Not applicable.
6 PERRE RW 0x0 Parity Error Enable. Not applicable.
7 ADSTEP RO 0x0 Address Data Stepping. Not applicable.
8 SERRE RW 0x0 SERR Enable. Non-fatal and fatal errors detected by the bridge
are reported to the Root Complex when this bit is set or the bits in
the PCI Express Device Control register are set (see PCIEDCTL
- PCI Express Device Control (0x048)).
In addition, when this bit is set it enables the forwarding of
ERR_NONFATAL and ERR_FATAL error messages from the
secondary to the primary interface. ERR_COR messages are
unaffected by this bit and are always forwarded.
0x0 -(disable) Disable non-fatal and fatal error reporting if also
disabled in Device Control register.
0x1 -(enable) Enable non-fatal and fatal error reporting.
9 FB2B RO 0x0 Fast Back-to-Back Enable. Not applicable.
10 INTXD RW 0x0 INTx Disable. Controls the ability of the PCI-PCI bridge to gener-
ate an INTx interrupt message.
When this bit is set, any interrupts generated by this bridge are
negated. This may result in a change in the resolved interrupt
state of the bridge.
This bit has no effect on interrupts forwarded from the secondary
to the primary interface.
15:11 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
2:0 Reserved RO 0x0 Reserved.
Bit
Field
Field
Name
Type
Default
Value
Description