IDT 89HPES16T4AG2, User Manual

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IDT Link Operation
PES16T4AG2 User Manual 3 - 6 May 23, 2013
Notes
Autonomous Link Reliability Management
As mentioned above, an unreliable link exhibits recurrent errors. When the rate of errors is very high, the
LTSSM will likely be unable to communicate with the link partner and automatically revert to the lowest
possible link speed (i.e., 2.5 Gbps). The mechanism to detect severe link errors and downgrade speed is
part of the PCIe 2.0 specification.
However, if the rate of link errors is low enough to keep the LTSSM operating in Gen2 mode, but high
enough that it adversely affects link bandwidth or compromises link stability (i.e., by constantly retraining
the link through the Recovery state), none of the mechanisms in the PCIe 2.0 specification can detect and
react appropriately.
As an example, a bit error rate of 1.0E-6 in Gen2 mode (i.e., 1 error every 200 usec) may result in a
large number of TLP replays on the link, which impact link bandwidth and potentially result in link retrain
events that move the link repeatedly through the Recovery state. A large number of link retrains not only
make the link bandwidth unpredictable, but can potentially bring the link down, resulting in system insta-
bility.
In order to address this, a mechanism is desired that monitors link errors such that when they reach a
programmable rate (i.e., 1.0E-6 as the example above), the mechanism is capable of autonomously down-
grading link speed, potentially enhancing link and bandwidth stability. The Autonomous Link Reliability
Management logic in the PES16T4AG2 is such a mechanism. Each PES16T4AG2 port has the capability to
autonomously detect link unreliability and react by downgrading the link speed to 2.5 Gbps.
This capability is enabled by setting the Enable (EN) bit of the Autonomous Link Reliability Control
register (ALRCTL). Once enabled, it remains enabled until the user clears the EN bit. By default, the ALR
mechanism is disabled. When enabled, the Autonomous Link Reliability logic monitors the rate of errors in
the link. When the rate of errors crosses an specified threshold, the Phy’s LTSSM downgrades the link
speed to 2.5 Gbps, removes support for 5.0 Gbps from its advertised data rate in training sets, and remains
in this downgraded data rate until the link fully retrains or the Link Retrain (LRET) field of the PCI Express
Link Control (PCIELCTL) register is set, when the target link speed is 5.0 Gbps.
The Autonomous Link Reliability Management logic is capable of monitoring two types of link error
conditions: individual bit errors (i.e., LCRC errors) or link state errors (i.e., Phy LTSSM transitions through
the Recovery state). Only one of these type of errors may be monitored at a time. The type of error moni-
tored is selected by programming the Link Error Type (LET) field in the ALRCTL register. A user who wishes
to count all LCRC errors (which don’t necessarily result in link retraining) can program the LET field appro-
priately. A user who wishes to count link retraining events caused by link errors can program the LET field to
LTSSM Recovery transitions.
1
As mentioned above, when the rate of errors crosses an specified threshold, the Phy’s LTSSM down-
grades the link speed. The threshold is programmed via the Autonomous Link Reliability Error Rate
Threshold (ALRERT) register. This register contains two fields: Error Threshold (ERRT) and Monitoring
Period (PERIOD). The PERIOD field is programmed in units of micro-seconds. The Autonomous Link Reli-
ability logic determines that a link is unreliable when it detects ERRT errors in PERIOD time. When this
occurs, the LTSSM downgrades the link speed to 2.5 Gbps
2
and sets the Unreliable Link Detected (ULD)
bit in the ALRSTS register
3
. Additionally, the LTSSM sets the Link Bandwidth Management Status
(LBWSTS) bit in the PCI Express Link Status (PCIELSTS) register.
4
1.
Note that it is only possible to count link errors that cause the PES16T4AG2 port to initiate a link transition to
Recovery. Link errors which cause the link partner to initiate entry into the Recovery state are not counted.
2.
This requires that the PHY LTSSM change its advertisement of supported link speeds to 2.5 Gbps only.
3.
The ULD bit is a status bit set by hardware. Once set, it will remain set until cleared by software. Hardware
never clears the ULD bit.
4.
Note that per the PCIe 2.0 specification, the LBWSTS bit is not set if the link transitions through the DL_Down
state.