IDT 89HPES16T4AG2, User Manual

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IDT Link Operation
PES16T4AG2 User Manual 3 - 4 May 23, 2013
Notes exchanged with the link partner during link training. A Downstream port link partner may autonomously
change link width. When this occurs, the PES16T4AG2 downstream port sets the Link Autonomous Band-
width Status (LABWSTS) bit in the PCIELSTS register.
Link Speed Negotiation
The PCIe 2.0 specification introduces support for 5.0 Gbps data rates per lane (Gen2), in addition to the
2.5 Gbps data rates (Gen1) mandated in previous versions of the specification. Per the PCIe 2.0 specifica-
tion, all lanes of a link must operate at the same data rate. During full link training, links initially operate at
2.5 Gbps. Once the LTSSM on both components of the link reaches the L0 state, the link speed may be
upgraded to 5.0 Gbps if this capability is advertised and desired by both components. The process of
upgrading the link speed does not result in a DL_Down state.
It is the responsibility of the upstream component of the link (i.e., switch downstream ports) to keep the
link at the target link speed or at the highest common speed supported by both components of the link. In
addition, either link component may request a link speed change due to software requests or link reliability
reasons (i.e., speed downgrade). Downstream components are further permitted to request link speed
changes due to autonomous hardware initiated mechanisms.
A component must only initiate a link speed change when it knows that its link partner supports the
target speed via prior exchange of Training Sets. As stated before, Gen2 support is optional while Gen1
support is mandatory. Also, a component may advertise supported link speeds via the Recovery state,
without necessarily changing the link speed.
If neither component in the link advertises support for Gen2, then the link remains operating in Gen1
speed. If one of the components decides to advertise support for Gen2 (i.e., software sets the Target link
Speed = Gen2), then this component will advertise its support for Gen2 speed via the Recovery state. The
link will continue to operate in Gen1 speed since only one of the components has advertised support for the
higher speed. If one component has advertised support for Gen1 and Gen2, and the other has advertised
support for Gen1 only, then the link will remain operating in Gen1 speed until the lesser-speed component
decides to:
– Advertise support for Gen2 via the Recovery state without modifying the link speed. The link
remains operating at Gen1 speed.
– Transition the link speed to Gen2 via the Recovery.Speed state. The link will operate at Gen2
speed. In this case, the advertisement of Gen2 speed by both components is done implicitly in the
Recovery substates entered while modifying the link speed.
Link Speed Negotiation in the PES16T4AG2
The PES16T4AG2 ports support per lane data rates of 5.0 Gbps and 2.5 Gbps. The highest data rate of
each link is determined dynamically, and depends on the following factors:
– Maximum link data rate supported by both components of the link
– The Target Link Speed set via the Link Control 2 Register (PCIELCTL2)
– The Hardware Autonomous Speed Disable (HASD) bit in the PCIELCTL2 register
– The reliability of the link at 5.0 Gbps
By default, the Target Link Speed (TLS) of each port is set to 5.0 Gbps. Therefore, the PES16T4AG2
ports advertise support for 5.0 Gbps during the link training process via training-sets. After a fundamental
reset, each port link trains to the L0 state at 2.5 Gbps. If the Target Link Speed indicates 5.0 Gbps (default
value), the PHY LTSSM automatically initiates link speed upgrade to 5.0 Gbps using the link speed change
mechanism described in the PCIe 2.0 specification. This occurs regardless of the setting of the Hardware
Autonomous Speed Disable (HASD) bit in the PCIELCTL2 register.
1
1.
Initial link speed upgrade is not considered an autonomous link speed upgrade, since it is caused by the default
setting of the Target Link Speed field in the PCIELCTL2 register.