IDT 89HPES16T4AG2 User Manual Download Page 92

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IDT Configuration Registers

PES16T4AG2 User Manual

8 - 10

May 23, 2013

Notes

Register Definitions

Type 1 Configuration Header Registers

VID - Vendor Identification Register (0x000)

DID - Device Identification Register (0x002)

PCICMD - PCI Command Register (0x004)

0x31C

Dword

Px_PWRBDV7

PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C)
on page 8-56

0x500

Dword

Px_SERDESCTL

SERDESCTL- SerDes Control (0x500) on page 8-67

0x530

Dword

Px_PHYLCFG0

PHYLCFG0 - Phy Link Configuration 0 (0x530) on page 8-67

0x538

Dword

Px_PHYLSTS0

PHYLSTS0 - Phy Link Status 0 (0x538) on page 8-68

0x540

Dword

Px_PHYLSTATE0

PHYLSTATE0 - Phy Link State 0 (0x540) on page 8-70

0x55C

Dword

Px_PHYPRBS

PHYPRBS - Phy PRBS Seed (0x55C) on page 8-71

0x560

Dword

Px_ALRCTL

ALRCTL - Autonomous Link Reliability Control (0x560) on page 8-71

0x564

Dword

Px_ALRSTS

ALRSTS - Autonomous Link Reliability Status (0x564) on page 8-72

0x568

Dword

Px_ALRERT

ALRERT - Autonomous Link Reliability Error Rate Threshold

(0x5680) on page 8-72

0x56C

Dword

Px_ALRCNT

ALRCNT - Autonomous Link Reliability Counter (0x56C) on page 8-

Bit

Field

Name

Type

Default

Value

Description

15:0

VID

0x111D

Vendor Identification.

This field contains the 16-bit vendor ID

value assigned to IDT.
See section Vendor ID on page 1-4.

Bit

Field

Name

Type

Default

Value

Description

15:0

DID

Device Identification.

This field contains the 16-bit device ID

assigned by IDT to this bridge.
See section Device ID on page 1-4.

Bit

Field

Name

Type

Default

Value

Description

IOAE

0x0

I/O Access Enable.

When this bit is cleared, the bridge does not

respond to I/O accesses from the primary bus specified by
IOBASE and IOLIMIT.
0x0 - (disable) Disable I/O space.
0x1 - (enable) Enable I/O space.

Cfg.

Offset

Size

Register

Mnemonic

Register Definition

Table 8.3 Downstream Ports 1 through 5 Configuration Space Registers (Part 5 of 5)

Summary of Contents for 89HPES16T4AG2

Page 1: ...024 Silver Creek Valley Road San Jose California 95138 Telephone 800 345 7015 408 284 8200 FAX 408 284 2775 Printed in U S A 2013 Integrated Device Technology Inc IDT 89HPES16T4AG2 PCI Express Switch...

Page 2: ...PLES CONTAINED IN ANY IDT PUBLICATION OR PUBLIC DISCLOSURE OR THAT IS CONTAINED ON ANY IDT INTERNET SITE IN NO EVENT WILL IDT BE LIABLE FOR ANY DIRECT CONSEQUENTIAL INCIDENTAL INDIRECT PUNITIVE OR SPE...

Page 3: ...or alternate functions Chapter 5 SMBus Interfaces describes the operation of the 2 SMBus interfaces on the PES16T4AG2 Chapter 6 Power Management describes the power management capability structure loc...

Page 4: ...1 D ABC x 2 D ABCyD Data Units The following data unit terminology is used in this document In quadwords bit 63 is always the most significant bit and bit 0 is the least significant bit In double wor...

Page 5: ...Write RCW Software can read the register bits with this attribute Reading the value will automatically cause the register bits to be reset to zero Writes cause the register bits to be modified Reserve...

Page 6: ...s RO and ARIFEN in PCIEDCTL2 is RO January 25 2008 Removed all reference to REFRES4 and REFRES5 pins May 30 2008 Added Device Number Configuration section to Chapter 1 and added DEVNUMCTL register to...

Page 7: ...uration and Downconfiguration September 15 2010 In Table 1 10 changed Buffer type for PCI Express from CML to PCIe differential and changed reference clocks to HCSL October 26 2010 In Chapter 2 revise...

Page 8: ...IDT PES16T4AG2 User Manual 6 May 23 2013 Notes...

Page 9: ...9 Port Configuration 1 10 Clocking Reset and Initialization Clocking 2 1 Initialization 2 1 Reset 2 2 Fundamental Reset 2 2 Hot Reset 2 4 Upstream Secondary Bus Reset 2 5 Downstream Secondary Bus Rese...

Page 10: ...es Introduction 5 1 Master SMBus Interface 5 2 Initialization 5 2 Serial EEPROM 5 2 I O Expanders 5 6 Slave SMBus Interface 5 13 Initialization 5 14 SMBus Transactions 5 14 Power Management Introducti...

Page 11: ...xpress Virtual Channel Capability 8 49 Power Budgeting Enhanced Capability 8 55 Switch Control and Status Registers 8 56 Autonomous Link Reliability Management 8 71 JTAG Boundary Scan Introduction 9 1...

Page 12: ...IDT Table of Contents PES16T4AG2 User Manual iv May 23 2013 Notes...

Page 13: ...Signals 5 10 Table 5 6 I O Expander 1 Signals 5 10 Table 5 7 I O Expander 2 Signals 5 12 Table 5 8 I O Expander 3 Signals 5 12 Table 5 9 I O Expander 4 Signals 5 13 Table 5 10 Slave SMBus Command Code...

Page 14: ...IDT List of Tables PES16T4AG2 User Manual vi May 23 2013 Notes...

Page 15: ...mat 5 15 Figure 5 7 Serial EEPROM Read or Write CMD Field Format 5 16 Figure 5 8 CSR Register Read Using SMBus Block Write Read Transactions with PEC Disabled 5 17 Figure 5 9 Serial EEPROM Read Using...

Page 16: ...IDT List of Figures PES16T4AG2 User Manual viii May 23 2013 Notes...

Page 17: ...ation Register 0x002 8 10 ECFGADDR Extended Configuration Space Access Address 0x0F8 8 39 ECFGDATA Extended Configuration Space Access Data 0x0FC 8 40 EEPROMINTF Serial EEPROM Interface 0x42C 8 63 ERO...

Page 18: ...te 0 0x540 8 70 PHYLSTS0 Phy Link Status 0 0x538 8 68 PHYPRBS Phy PRBS Seed 0x55C 8 71 PLTIMER Primary Latency Timer 0x00D 8 13 PMBASE Prefetchable Memory Base Register 0x024 8 16 PMBASEU Prefetchable...

Page 19: ...e 0 Capability 0x210 8 51 VCR0CTL VC Resource 0 Control 0x214 8 51 VCR0STS VC Resource 0 Status 0x218 8 52 VCR0TBL0 VC Resource 0 Arbitration Table Entry 0 0x220 8 53 VCR0TBL1 VC Resource 0 Arbitratio...

Page 20: ...IDT Register List PES16T4AG2 User Manual xii May 23 2013 Notes...

Page 21: ...or x1 Automatic lane reversal on all ports Automatic polarity inversion Configurable downstream port PCI to PCI bridge device numbering Ability to load device configuration from serial EEPROM Legacy S...

Page 22: ...Figure 1 1 PES16T4AG2 Architectural Block Diagram TDM Demux D Bus U Bus ESP Arb ESP Arb ESP Arb ESP Arb Route Map Table Ingress Processor TLP Checker Egress Processor Completion Processor Message Proc...

Page 23: ...E0RN 0 PE0RP 3 PE0RN 3 PCI Express Switch SerDes Input PE0TN 0 PE0TP 3 PE0TN 3 PCI Express Switch SerDes Output Port 0 Port 0 PE1RP 0 PE1RN 0 PE1RP 3 PE1RN 3 PCI Express Switch SerDes Input PE1TP 0 PE...

Page 24: ...Subsystem Vendor ID capability structure However in the default configuration the Subsystem ID and Subsystem Vendor ID capability structure is not enabled To enable the capability the SSID and SSVID...

Page 25: ...N 3 0 I PCI Express Port 2 Serial Data Receive Differential PCI Express receive pairs for port 2 PE2TP 3 0 PE2TN 3 0 O PCI Express Port 2 Serial Data Transmit Differential PCI Express trans mit pairs...

Page 26: ...tion pin type Output Alternate function Reset output for downstream port 3 GPIO 10 I O General Purpose I O This pin can be configured as a general purpose I O pin Table 1 5 General Purpose I O Pins Si...

Page 27: ...ifted out from the boundary scan logic or JTAG Controller When no data is being shifted out this signal is tri stated JTAG_TMS I JTAG Mode The value on this signal controls the test mode select of the...

Page 28: ...ected from this pin to ground VDDCORE I Core VDD Power supply for core logic VDDI O I I O VDD LVTTL I O buffer power supply VDDPEA I PCI Express Analog Power Serdes analog power supply 1 0V VDDPEHA I...

Page 29: ...rface PE0RN 3 0 I PCIe differential2 Serial Link PE0RP 3 0 I PE0TN 3 0 O PE0TP 3 0 O PE1RN 3 0 I PE1RP 3 0 I PE1TN 3 0 O PE1TP 3 0 O PE2RN 3 0 I PE2RP 3 0 I PE2TN 3 0 O PE2TP 3 0 O PE3RN 3 0 I PE3RP 3...

Page 30: ...G2 s virtual PCI bus are treated by the upstream port port 0 as an unsupported request i e the device no longer exists This renders the registers in port y s configuration space inaccessible to the ro...

Page 31: ...tion the PES16T4A operates as a 2 port switch with each port having a x8 width Figure 1 3 All Ports Unmerged Configuration Figure 1 4 Two Ports Merged Configuration PES16T4AG2 PCI to PCI Bridge PCI to...

Page 32: ...16T4AG2 Device Overview PES16T4AG2 User Manual 1 12 May 23 2013 Notes Figure 1 5 All Ports Merged Configuration PES16T4AG2 PCI to PCI Bridge PCI to PCI Bridge Dev 2 Dev 0 Port 0 Virtual PCI Bus x8 Por...

Page 33: ...rride the function of some of the signals in the boot configuration vector during a Fundamental Reset The signals that may be over ridden are noted in Table 2 1 The state of all of the boot configurat...

Page 34: ...in normal mode the following reset sequence is executed 1 Wait for the Fundamental Reset condition to clear e g negation of PERSTN Note that PERSTN must be asserted for at least 100ms Tpvperl after t...

Page 35: ...device operation begins The PCIe specification indicates that a device must respond to Configuration Request transactions within 100 ms from the end of Conventional Reset cold warm or hot Additionally...

Page 36: ...to scale 2 The PES16T4AG2 requires a minimum time for Tperst clk of 1 s The PES16T4AG2 requires a minimum time for Tpvperl of 1ms 3 In a system the values of Tpvperl and Tperst clk depend on the mech...

Page 37: ...Reset Serial EEPROM Initialization DHRSTSEI bit is not set in the Switch Control SWCTL register the contents of the serial EEPROM are read and the appropriate PES16T4AG2 registers are updated If a one...

Page 38: ...r s default value to be returned on a read and written data to be ignored on writes Downstream Secondary Bus Reset A Downstream Secondary Bus Reset may be initiated by the following condition A one is...

Page 39: ...ower to Reset Negation PWR2RST field in the HPCFGCTL register While slot power is enabled the corresponding downstream port reset output is negated When slot power is disabled by writing a one to the...

Page 40: ...n the Reset Negation to Slot Power RST2PWR field in the HPCFGCTL register If at any point while a downstream port is not being reset i e PxRSTN is negated a power fault is detected i e PxPWRGDN is neg...

Page 41: ...logic for the receiving lane automatically inverts received data Polarity inversion is a lane and not a link function Therefore it is possible for some lanes of link to be inverted and for others to n...

Page 42: ...without lane reversal PExRP 0 PExRP 1 PExRP 2 PExRP 3 PExRP 4 PExRP 5 PExRP 6 PExRP 7 PES16T4AG2 lane 7 lane 6 lane 5 lane 4 lane 3 lane 2 lane 1 lane 0 b x8 Port with lane reversal PExRP 0 PExRP 1 PE...

Page 43: ...ownconfigured if a partic ular lane is determined to be unreliable With dynamic link width upconfiguration the system designer can choose to connect components with enough lanes to handle worst case b...

Page 44: ...rtise support for Gen2 i e software sets the Target link Speed Gen2 then this component will advertise its support for Gen2 speed via the Recovery state The link will continue to operate in Gen1 speed...

Page 45: ...Gbps may be down graded to 2 5 Gbps As mentioned above the Target Link Speed TLS field of the Link Control 2 Register PCIELCTL2 sets the preferred link speed By default the Target Link Speed of each p...

Page 46: ...s the link speed to 2 5 Gbps removes support for 5 0 Gbps from its advertised data rate in training sets and remains in this downgraded data rate until the link fully retrains or the Link Retrain LRET...

Page 47: ...ining can be done autonomously in response to link problems i e repeated TLP replay attempts or as a result of software setting the link retrain LRET bit in the PCI Express Link Control PCIELCTL regis...

Page 48: ...it value from a downstream switch port or root port to the upstream port of a connected device or switch Upstream Port When a Set_Slot_Power_Limit message is received by the upstream switch port then...

Page 49: ...to transmit on the upstream port or there are no available flow control credits to transmit a TLP There are no DLLPs pending for transmission on the upstream port The downstream switch ports have the...

Page 50: ...h upstream port or endpoint advertises its desired de emphasis by transmission of training sets The upstream compo nent of the link i e switch downstream port or root complex port notes its link partn...

Page 51: ...g the GPIO pins as outputs since an incorrect configuration could cause damage to external components as well as the PES16T4AG2 GPIO Configuration Associated with each GPIO pin is a bit in the GPIOFUN...

Page 52: ...ster is driven on the pin System designers should treat the GPIO outputs as asynchronous outputs The actual value of the output pin can be determined by reading the GPIOD register GPIO Pin Configured...

Page 53: ...nd slave SMBuses may be used in a unified or split configuration Figure 5 1 SMBus Interface Configuration Examples In the unified configuration shown in Figure 5 1 a the master and slave SMBuses are t...

Page 54: ...responding registers in the PES16T4AG2 Any PES16T4AG2 software visible register in any port may be initialized with values stored in the serial EEPROM Each software visible register in the PES16T4AG2...

Page 55: ...al CSR system address which is a byte address equals this value with two lower zero bits appended The next field is the TYPE field that indicates the type of the configuration block For single double...

Page 56: ...re 5 4 Configuration Done Sequence Format The checksum in the configuration done sequence enables the integrity of the serial EEPROM initializa tion to be verified Since uninitialized EEPROMs typicall...

Page 57: ...sy then the read operation may be initiated by performing a write to the Data DATA field When the serial EEPROM read operation completes the Done DONE bit in the EEPROMINTF register is set and the bus...

Page 58: ...o each I O expander used in that system configuration should be written to the corresponding IO Expander Address IOE 0 4 ADDR field The IOE 0 3 ADDR fields are contained in the I O Expander Address 0...

Page 59: ...tain the current state of the lower eight I O expander bits i e I O 0 0 through I O 0 7 Read value of I O expander register 1 to obtain the current state of the upper eight I O expander bits i e I O 1...

Page 60: ...on the board and connected to GPIO 2 Whenever IOEXPINTN0 is asserted the PES16T4AG2 reads the state of all I O expanders For compatibility with legacy Gen 1 PCIe switches the PES16T4AG2 supports indiv...

Page 61: ...sue is with the interrupt logic The IO Expander Test Mode IOEXTM bit in the IOEXPTINF register allows an I O expander test mode to be entered When this bit is set the PES16T4AG2 core logic outputs are...

Page 62: ...nterlock 8 I O 1 0 I P4APN Unused 9 I O 1 1 I P4PDN Unused 10 I O 1 2 I P4PFN Unused 11 I O 1 3 I P4MRLN Unused 12 I O 1 4 O P4AIN Unused 13 I O 1 5 O P4PIN Unused 14 I O 1 6 O P4PEP Unused 15 I O 1 7...

Page 63: ...3 I P5MRLN Unused 12 I O 1 4 O P5AIN Unused 13 I O 1 5 O P5PIN Unused 14 I O 1 6 O P5PEP Unused 15 I O 1 7 O P5ILOCKP Unused 1 I O x y corresponds to the notation used for PCA9555 port x I O pin y SMB...

Page 64: ...power good input 10 I O 1 2 I P2PWRGDN Port 2 power good input 11 I O 1 3 I P3PWRGDN Port 3 power good input 12 I O 1 4 I P4PWRGDN Unused 13 I O 1 5 I P5PWRGDN Unused 14 I O 1 6 I Unused 15 I O 1 7 I...

Page 65: ...PCA9555 port x I O pin y SMBus I O Expander Bit Type Signal Description 0 I O 0 0 1 1 I O x y corresponds to the notation used for PCA9555 port x I O pin y O P0LINKUPN Port 0 link up status output 1...

Page 66: ...escribed individually in the following sections If a command is issued while one is already in progress or if the slave is unable to supply data associated with a command the command is NACKed This in...

Page 67: ...icates the number of bytes following the byte count field when performing a write or setting up for a read The byte count field is also used when returning data to indi cate the number of following by...

Page 68: ...ithout error Byte Position Field Name Description 0 CCODE Command Code Slave Command Code field described in Table 5 10 1 BYTCNT Byte Count The byte count field is only transmitted for block type SMBu...

Page 69: ...transaction when accessing the serial EEPROM This bit has the same function as the NAERR bit in the SMBUSSTS reg ister The setting of this bit may indicate the following that the addressed device doe...

Page 70: ...SMBus Address Rd ADDRU A BYTCNT 5 A EEADDR CMD status A A A N DATA ADDRU A P ADDRL A S PES16T4AG2 Slave SMBus Address Wr A N CCODE START END P PES16T4AG2 not ready with data S PES16T4AG2 Slave SMBus...

Page 71: ...S PES16T4AG2 Slave SMBus Address Rd DATALM DATALL A N P P S PES16T4AG2 Slave SMBus Address Wr A A ADDRU A CCODE END Byte P A S PES16T4AG2 Slave SMBus Address Wr A CCODE Byte A P A S PES16T4AG2 Slave S...

Page 72: ...IDT SMBus Interfaces PES16T4AG2 User Manual 5 20 May 23 2013 Notes...

Page 73: ...entire device When the upstream port enters a low power state and the PME_TO_Ack messages are received then the entire device is placed into a low power state The PES16T4AG2 supports the following dev...

Page 74: ...s includes both the case when the downstream port is in the D3hot state or the entire switch is in the D3hot state The generation of a PME message by downstream ports necessitates the implementation o...

Page 75: ...ort that does not receive a PME_TO_Ack message in the time out period specified in the PME_TO_Ack Time Out PMETOATO field in its corresponding PME_TO_Ack Timer PMETOATIMER register declares a time out...

Page 76: ...IDT Power Management PES16T4AG2 User Manual 6 4 May 23 2013 Notes...

Page 77: ...pstream port serves as the add in card s PCIe interface In this application the upstream port may be hot plugged into a slot on the main system Finally Figure 7 3 illustrates the use of the PES16T4AG2...

Page 78: ...is implemented or on the add in board When located on the add in board state changes are communicated between the hot plug controller asso ciated with the slot and the add in card via hot plug message...

Page 79: ...ce detect The Presence Detect Control PDETECT field in the Hot Plug Configuration Control HPCFGCTL register may be used to control the mechanism used for presence detect Since the polarity of hot plug...

Page 80: ...e train the link starting from the Detect state When this occurs the Hot Plug controller for the port does not set the Presence Detect Changed PDC bit in the PCIESSTS register Hot Plug I O Expander Th...

Page 81: ...hot plug event through assertion of the GPEN signal the corresponding port s status bit in the General Purpose Event Status P0_GPESTS register is set A bit in the P0_GPESTS register can only be set if...

Page 82: ...mary the PES16T4AG2 meets all of the I O requirements necessary to build a PICMG compliant hot swap board or system The hot swap I O buffers of the PES16T4AG2 may also be used to construct proprietary...

Page 83: ...ror reporting via interrupts is an optional capability the MSI capability structure associated with the upstream port is not by default part of the PCI capability structure linked list Reading from an...

Page 84: ...ass Code Register 0x009 on page 8 12 0x00C Byte P0_CLS CLS Cache Line Size Register 0x00C on page 8 13 0x00D Byte P0_PLTIMER PLTIMER Primary Latency Timer 0x00D on page 8 13 Table 8 2 Upstream Port 0...

Page 85: ...DWord P0_PMLIMITU PMLIMITU Prefetchable Memory Limit Upper Register 0x02C on page 8 17 0x030 Word P0_IOBASEU IOBASEU I O Base Upper Register 0x030 on page 8 17 0x032 Word P0_IOLIMITU IOLIMITU I O Lim...

Page 86: ...page 8 39 0x0F8 Dword P0_ECFGADDR ECFGADDR Extended Configuration Space Access Address 0x0F8 on page 8 39 0x0FC Dword P0_ECFGDATA ECFGDATA Extended Configuration Space Access Data 0x0FC on page 8 40...

Page 87: ...Arbitration Table Entry 3 0x22C on page 8 54 0x280 Dword P0_PWRBCAP PWRBCAP Power Budgeting Capabilities 0x280 on page 8 55 0x284 Dword P0_PWRBDSEL PWRBDSEL Power Budgeting Data Select 0x284 on page 8...

Page 88: ...8 67 0x530 Dword P0_PHYLCFG0 PHYLCFG0 Phy Link Configuration 0 0x530 on page 8 67 0x538 Dword P0_PHYLSTS0 PHYLSTS0 Phy Link Status 0 0x538 on page 8 68 0x540 Dword P0_PHYLSTATE0 PHYLSTATE0 Phy Link St...

Page 89: ...efetchable Memory Limit Register 0x026 on page 8 17 0x028 DWord Px_PMBASEU PMBASEU Prefetchable Memory Base Upper Register 0x028 on page 8 17 0x02C DWord Px_PMLIMITU PMLIMITU Prefetchable Memory Limit...

Page 90: ...7 0x0D0 DWord Px_MSICAP MSICAP Message Signaled Interrupt Capability and Control 0x0D0 on page 8 37 0x0D4 DWord Px_MSIADDR MSIADDR Message Signaled Interrupt Address 0x0D4 on page 8 38 0x0D8 DWord Px_...

Page 91: ...pability 0x210 on page 8 51 0x214 DWord Px_VCR0CTL VCR0CTL VC Resource 0 Control 0x214 on page 8 51 0x218 DWord Px_VCR0STS VCR0STS VC Resource 0 Status 0x218 on page 8 52 0x280 Dword Px_PWRBCAP PWRBCA...

Page 92: ...mous Link Reliability Status 0x564 on page 8 72 0x568 Dword Px_ALRERT ALRERT Autonomous Link Reliability Error Rate Threshold 0x5680 on page 8 72 0x56C Dword Px_ALRCNT ALRCNT Autonomous Link Reliabili...

Page 93: ...ty Error Enable Not applicable 7 ADSTEP RO 0x0 Address Data Stepping Not applicable 8 SERRE RW 0x0 SERR Enable Non fatal and fatal errors detected by the bridge are reported to the Root Complex when t...

Page 94: ...le 10 9 DEVT RO 0x0 DEVSEL TIming Not applicable 11 STAS RO 0x0 Signalled Target Abort Not applicable since a target abort is never signalled 12 RTAS RO 0x0 Received Target Abort Not applicable 13 RMA...

Page 95: ...field has no effect on the bridge s func tionality but may be read and written by software This field is implemented for compatibility with legacy software Bit Field Field Name Type Default Value Des...

Page 96: ...the primary interface of the bridge is connected This field has no functional effect within the PES16T4AG2 but is implemented as a read write register for software compatibility Bit Field Field Name T...

Page 97: ...g This bit always reflects the value of the IOCAP field in the IOBASE register 3 1 Reserved RO 0x0 Reserved field 7 4 IOLIMIT RW 0x0 I O Limit The IOBASE and IOLIMIT registers are used to control the...

Page 98: ...RW 0x0 Memory Address Limit The MBASE and MLIMIT registers are used to control the forwarding of non prefetchable transactions between the primary and secondary interfaces of the bridge This field co...

Page 99: ...ield contains A 31 20 of the highest memory address with A 19 0 assumed to be 0xF_FFFF that is below the primary interface of the bridge PMLIMITU specifies the remaining bits Bit Field Field Name Type...

Page 100: ...Bit Field Field Name Type Default Value Description 7 0 CAPPTR RWL 0x40 Capabilities Pointer This field specifies a pointer to the head of the capabilities structure Bit Field Field Name Type Default...

Page 101: ...System Error Enable This bit controls forwarding of ERR_COR ERR_NONFATAL ERR_FATAL from the secondary interface of the bridge to the primary interface Note that error reporting must be enabled in the...

Page 102: ...uired to update port status 15 7 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 7 0 CAPID RO 0x10 Capability ID The value of 0x10 identifies this capability as a PC...

Page 103: ...n endpoint can withstand due to transition from the L1 state to the L0 state The value is hardwired to 0x0 as this field does not apply to a switch 12 ABP RO 0x0 Attention Button Present In PCIe base...

Page 104: ...icable to the switch since the switch never sets the relaxed ordering bit in transactions it initiates as a requester Therefore this bit is hardwired to 0x0 7 5 MPS RW 0x0 Max Payload Size This field...

Page 105: ...indicates the status of cor rectable errors Errors are logged in this register regardless of whether error reporting is enabled or not 1 NFED RW1C 0x0 Non Fatal Error Detected This bit indicates the...

Page 106: ...s and L1 are supported 14 12 L0SEL RWL 0x6 L0s Exit Latency This field indicates the L0s exit latency for the given PCI Express link 17 15 L1EL RWL 0x2 L1 Exit Latency This field indicates the L1 exit...

Page 107: ...ame Type Default Value Description 1 0 ASPM RW 0x0 Active State Power Management ASPM Control This field controls the level of ASPM supported by the link The initial value corresponds to disabled The...

Page 108: ...er The LTRAIN bit is set at a 1ms delay 6 CCLK RW 0x0 Common Clock Configuration When set this bit indicates that this component and the component at the opposite end of the link are operating with a...

Page 109: ...is unable to train the value in this field is set to 0x0 10 TERR RO 0x0 Training Error In PCIe base 1 0a when set this bit indicates that a link training error has occurred The value of this field is...

Page 110: ...red to zero This field is hardwired to zero in the upstream port 15 LABWSTS RW1C 0x0 Link Autonomous Bandwidth Status This bit is set to indicate that either that the PHY has autonomously changed link...

Page 111: ...s written or when the link transitions from a non DL_Up status to a DL_Up status This bit is read only and has a value of zero when the SLOT bit in the PCIECAP register is cleared 16 15 SPLS RW 0x0 Sl...

Page 112: ...ted Changed Enable This bit when set enables the generation of a Hot Plug interrupt or wake up event on a presence detect change event This bit is read only and has a value of zero when the corre spon...

Page 113: ...Power on 0x1 off Power off 11 EIC RW 0x0 Electromechanical Interlock Control This field always returns a value of zero when read If an electromechanical interlock is implemented a write of a one to th...

Page 114: ...t and reflects the state of the Presence Detect status 0x0 empty Slot empty 0x1 present Card present 7 EIS RO 0x0 Electromechanical Interlock Status When an electromechani cal interlock is implemented...

Page 115: ...Field Name Type Default Value Description 15 0 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 31 0 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default...

Page 116: ...d to modify the de emphasis setting on the line i e Recovery Speed Therefore after modifying this field it is recommended that the link be fully retrained by setting the FLRET bit in the PHYLSTATE0 re...

Page 117: ...DE RW 0x0 Sticky Compliance De emphasis This bit selects the de emphasis value in the Polling Compliance state when this state was entered as a result of setting the Enter Compliance ECOMP bit in this...

Page 118: ...e with version two of the specification Complies with version the PCI Bus Power Management Interface Specification Revision 1 2 19 PMECLK RO 0x0 PME Clock Does not apply to PCI Express 20 Reserved RO...

Page 119: ...t is set PME message generation is enabled for the port If a hot plug wake up event is desired when exiting the D3cold state then this bit should be set during serial EEPROM initializa tion A hot rese...

Page 120: ...te transaction The PES16T4AG2 assumes that all downstream port generated MSIs are targeted to the root and routes these transactions to the upstream port Configuring the address contained in a down st...

Page 121: ...ucture 15 8 NXTPTR RWL 0x00 Next Pointer This field contains a pointer to the next capability structure 31 16 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 15 0 SS...

Page 122: ...ter SMBus reads of this field return a value of zero and SMBus writes have no effect Bit Field Field Name Type Default Value Description 15 0 CAPID RO 0x1 Capability ID The value of 0x1 indicates an a...

Page 123: ...iolation is detected on the port The PES16T4AG2 does not support ACS and therefore this bit is hardwired to 0x0 30 22 Reserved RO 0x0 Reserved field 31 DBE RW1C 0x0 Sticky Double Bit Error Status When...

Page 124: ...ility structure the First Error Pointer field FEPTR in the AERCTL register is not updated and an error is not reported to the root complex This bit does not affect the state of the corresponding bit i...

Page 125: ...ty structure the First Error Pointer field FEPTR in the AERCTL register is not updated and an error is not reported to the root complex This bit does not affect the state of the corresponding bit in t...

Page 126: ...ntrol Protocol Error Severity If the corresponding event is not masked in the AERUEM register then when the event occurs this bit controls the severity of the reported error If this bit is set the eve...

Page 127: ...ent is not masked in the AERUEM register then when the event occurs this bit controls the severity of the reported error If this bit is set the event is reported as a fatal error When this bit is clea...

Page 128: ...responding event is not reported to the root complex 7 BADDLLP RW 0x0 Sticky Bad DLLP Mask When this bit is set the corresponding bit in the AERCES register is masked When a bit is masked in the AERCE...

Page 129: ...ult Value Description 4 0 FEPTR RO 0x0 Sticky First Error Pointer This field contains a pointer to the bit in the AERUES register that resulted in the first reported error 5 ECRCGC RWL 0x1 ECRC Genera...

Page 130: ...d of the TLP header that resulted in the first reported uncorrectable error Bit Field Field Name Type Default Value Description 15 0 CAPID RO 0x3 Capability ID The value of 0x3 indicates a device seri...

Page 131: ...on 2 0 EVCCNT RO 0x0 Extended VC Count The value 0x0 indicates only implementa tion of the default VC 3 Reserved RO 0x0 Reserved field 6 4 LPEVCCNT RO 0x0 Low Priority Extended VC Count The value of 0...

Page 132: ...address of the Virtual Channel Capability structure in double quad words 16 bytes The value of zero indicates that the VC arbitration table is not present Bit Field Field Name Type Default Value Descr...

Page 133: ...d round robin with 128 phases bit 5 weighted round robin with 256 phases 13 8 Reserved RO 0x0 Reserved field 14 APS RO 0x0 Advanced Packet Switching Not supported 15 RJST RO 0x0 Reject Snoop Transacti...

Page 134: ...d 26 24 VCID RO 0x0 VC ID This field assigns a VC ID to the VC resource Since the PES16T4AG2 implements only a single VC this field is hard wired to zero 30 27 Reserved RO 0x0 Reserved field 31 VCEN R...

Page 135: ...arbitration period 15 12 PHASE3 RW 0x4 Phase 3 This field contains the port ID for the corresponding port arbitration period 19 16 PHASE4 RW 0x5 Phase 4 This field contains the port ID for the corresp...

Page 136: ...the port ID for the corresponding port arbitration period 15 12 PHASE19 RW 0x6 Phase 19 This field contains the port ID for the corresponding port arbitration period 19 16 PHASE20 RW 0x7 Phase 20 This...

Page 137: ...apability ID The value of 0x4 indicates a power budgeting capability structure If the power budgeting capability is used then this field should be initialized with data from a serial EEPROM 19 16 CAPV...

Page 138: ...r data for this device should be ignored If the power budgeting capability is used then this field should be initialized with data from a serial EEPROM 31 1 Reserved RO 0x0 Reserved field Bit Field Fi...

Page 139: ...rt 3 27 23 Reserved RO 0x0 Reserved field 31 28 MARKER RW 0x0 Sticky Marker This field is preserved across a hot reset and is available for general software use A hot reset does not result in modifica...

Page 140: ...et the Power Budgeting Data Value 7 0 PWRBDV 7 0 registers in all ports may be read and written When this bit is cleared then the PWRBDV registers in all ports are read only 5 DLDHRST RW 0x0 Sticky Di...

Page 141: ...fied device number 0x2 none All TLPs are delivered to the device attached to a link associated with a downstream switch port regardless of the specified device number 0x3 reserved 11 EUIDC RW 0x0 Stic...

Page 142: ...of the PxILOCKP output is inverted in all ports 8 IPXPWRGDN RW 0x0 Sticky Invert Polarity of PxPWRGDN When this bit is set the polarity of the PxPWRGDN input is inverted in all ports 10 9 PDETECT RW 0...

Page 143: ...x2 Reserved 0x3 Reserved 23 16 PWR2RST RW 0x14 Sticky Slot Power to Reset Negation This field contains the delay from stable downstream port power to negation of the down stream port reset in units of...

Page 144: ...function or GPIO pin Writing a value to this field causes the corresponding pins which are configured as GPIO outputs to change state to the value written 31 16 Reserved RO 0x0 Reserved field Bit Fie...

Page 145: ...a clock prescalar value used during master SMBus transactions The prescalar clock period is equal to 32 ns multiplied by the value in this field When the field is cleared to zero or one the clock is...

Page 146: ...lue Description 15 0 IOEDATA RW 0x0 I O Expander Data Each bit in this field corresponds to an I O expander input output signal Reading this field returns the cur rent value of the corresponding I O p...

Page 147: ...Bus transaction updating the I O expander outputs completes An I O Expander Address IOExADDR field is written in an SMBus I O Expander Address IOEXPADRy register the corre sponding I O expander is sel...

Page 148: ...s bit is set the hot plug INTx MSI and PME event notification mechanisms defined by the PCIe base 2 0 specification are disabled for port 1 and are instead signalled through General Purpose Event GPEN...

Page 149: ...is signalling a general purpose event by asserting the GPEN signal This bit is never set if the correspond ing general purpose event is not enabled in the GPECTL register GPEN is an alternate function...

Page 150: ...th x8 0x4 Reserved 0x5 Reserved 0x6 Reserved 0x7 Target Link Width Maximum Link Width MAXLNK WDTH in the PCIELCAP register When performing link width downconfiguration the value in this field must be...

Page 151: ...nk width was not re configured This field may be used by software to determine the success of dynamic upconfiguration or downconfiguration of links Please refer to section Dynamic Link Width Reconfigu...

Page 152: ...WAIT 0xB CFG_LNUM_ACCEPT 0xC CFG_COMPLETE 0xD CFG_IDLE 0xE RESERVE_2 0xF OVR_TMOUT 0x10 REC_RCVR_LOCK 0x11 REC_RCVR_CFG 0x12 REC_IDLE 0x13 REC_SPEED 0x14 L0 0x15 L0s 0x16 L1_ENTRY 0x17 L1_IDLE 0x18 L2...

Page 153: ...nomous Link Reliability Management on page 3 6 is enabled 0x0 Autonomous Link Reliability Management Disabled 0x1 Autonomous Link Reliability Management Enabled 1 LET RW 0x0 Sticky Link Error Type Thi...

Page 154: ...d by hardware 31 1 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 7 0 ERRT RW 0xFF Sticky Error Threshold The value in this field represents the mini mum number of...

Page 155: ...ERT register This count remains active when the ALR mechanism is dis abled Please refer to section Autonomous Link Reliability Manage ment on page 3 6 for further details 31 8 MPCNT RO 0x0 Monitoring...

Page 156: ...IDT Configuration Registers PES16T4AG2 User Manual 8 74 May 23 2013 Notes...

Page 157: ...AG2 Test Access Point The system logic utilizes a 16 state TAP controller a six bit instruction register and five dedicated pins to perform a variety of functions The primary use of the JTAG TAP Contr...

Page 158: ...active low Asynchronous reset for JTAG TAP controller internal pull up JTAG_TCK Input JTAG Clock Test logic clock JTAG_TMS and JTAG_TDI are sampled on the rising edge JTAG_TDO is output on the fallin...

Page 159: ...PE1TP 3 0 O PE2RN 3 0 I O PE2RP 3 0 I O PE2TN 3 0 O C PE2TP 3 0 O PE3RN 3 0 I O PE3RP 3 0 I O PE3TN 3 0 O C PE3TP 3 0 O PEREFCLKN I PEREFCLKP I SMBus MSMBCLK I O O C MSMBDAT I O O C SSMBCLK I O O C SS...

Page 160: ...ter s output latches is immediately transferred to the corresponding outputs or output enables Therefore the SAMPLE PRELOAD instruction must first be used to load suitable values into the boundary sca...

Page 161: ...utput Enable Cell is driving a high out to the pad which enables the pad for output and EXTEST is disabled the Capture Cell will be configured to capture output data from the core to the pad However i...

Page 162: ...troller passes through the UPDATE DR state these values will be latched onto the output pins or into the output enables Instruction Definition Opcode EXTEST Mandatory instruction allowing the testing...

Page 163: ...his register to devices further down stream IDCODE The IDCODE instruction is automatically loaded when the TAP controller state machine is reset either by the use of the JTAG_TRST_N signal or by the a...

Page 164: ...uctions Usage Considerations As previously stated there are internal pull ups on JTAG_TRST_N JTAG_TMS and JTAG_TDI However JTAG_TCK also needs to be driven to a known value It is best to either drive...

Page 165: ...e intended for developers skilled in the art designing with Renesas products You are solely responsible for 1 selecting the appropriate products for your application 2 designing validating and testing...

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