IDT 89HPES16T4AG2, User Manual

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IDT Configuration Registers
PES16T4AG2 User Manual 8 - 27 May 23, 2013
Notes
PCIELSTS - PCI Express Link Status (0x052)
15:12 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
3:0 CLS RO 0x1 Current Link Speed . This field indicates the current link speed of
the port.
1 - (gen1) 2.5 Gbps
2 - (gen2) 5 Gbps
others - reserved
9:4 NLW RO HWINIT Negotiated Link Width . This field indicates the negotiated width
of the link.
00 0001b - x1
00 0010b - x2
00 0100b - x4
00 1000b - x8
00 1100b - x12
01 0000b - x16
10 0000b - x32
When the MAXLNKWDTH field in the PCIELCAP register selects
a width not supported by the port, the value of this field corre-
sponds to the setting of the MAXLNKWDTH field, regardless of
the actual negotiated link width.
When the MAXLNKWDTH field in the PCIELCAP register selects
a width supported by the port, but the link is unable to train, the
value in this field is set to 0x0.
10 TERR RO 0x0 Training Error. In PCIe base 1.0a when set, this bit indicates
that a link training error has occurred.
The value of this field is undefined in the PCIe base 2.0 specifica-
tion.
11 LTRAIN RO 0x0 Link Training . When set, this bit indicates that link training is in
progress.
This bit is set when the Physical Layer LTSSM is in Configuration
or Recovery State, or when 0x1 is written to LRET bit in the
PCIELCTL register but Link training has not yet begun. For
upstream port, LRET has a delayed effect of 1 ms.
Hardware clears this bit when LTSSM exits Configuration/
Recovery State.
12 SCLK RWL HWINIT Slot Clock Configuration . When set, this bit indicates that the
component uses the same physical reference clock that the plat-
form provides. The initial value of this field is the state of the
CCLKUS signal for the upstream port and the CCLKDS signal for
downstream ports. The serial EEPROM may override these
default values.
Bit
Field
Field
Name
Type Default
Value
Description