HP 64782, User Manual, Page: 504 / 554

Concepts of Show Cycles
Typically when the processor accesses internal resources (either the Module
Control Block, or internal RAM) the bus cycles are not available external to
the processor. These bus cycles can be made available by enabling a feature
of the 6833x processor called show cycles. In order to capture a trace of
activity involving these internal resources, the 6833x processor’s show cycles
feature is used to make activity available to the analyzer. Two two control
bits in the SIM_MCR register must be set to enable the show cycles feature.
Specifically, these control bits are bits 8 and 9 of the Module Control
Register. These two bits control external bus arbitration in addition to show
cycles. Refer to the
Motorola 6833x User Manual for detailed information
of how to program these bits.
The external-bus decoder within the emulator will automatically decode
these "show" bus cycles if the following two conditions are met.
•
Condition 1: Show cycles are enabled as described above.
•
Condition 2: The /DS signal is available external to the processor.
If the pin that carries the /DS signal is programmed as a portE I/O pin, the
processor is not able to indicate a show cycle and the analyzer will not be
able to display show cycles in a trace.
The external-bus decoder within the emulator will automatically decode
these "show" bus cycles so the emulation-bus analyzer can correctly capture
them. Note that the external-bus decoder can only correctly decode one
internal RAM space at a time. For processors with multiple internal RAM
spaces, the emulator user must select which RAM space will be decoded by
answering a configuration question.
If an emulated processor has two internal RAM spaces enabled at the same
time, one at address 0, and one at address 0x200000, a configuration question
will ask you which internal RAM space to decode. If you answer the one at
address 0, then when execution is within the range controlled by the internal
RAM at address 0, decoding will be correct. When execution is within the
range controlled by the RAM at address 0x200000, captured address
information will not be correct; address information will indicate that the
accessed addresses were within the range beginning at 0, not 0x200000.
Note that even though the upper address information will be incorrect, all
other information in the trace will be correct.
Concepts
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