HP 64782, User Manual, Page: 208 / 554

Emulation Analyzer Trace Signals
Trace
Signals Analyzer
Channel # Signal
Name Signal
Description
bit 8
bit 9 ch 56
ch 57 DSACK0
DSACK1 These are processor DSACK signals, which may be
configured as I/O pins.
bit 10 ch 58 BERR 0 = bus error
1 = no bus error
bit 11 ch 59 HALT 0 = processor halt
1 = processor is not halted
bit 12 ch 60 CODE 0 = instruction fetch
1 = data transfer
bit 13 ch 61 FLUSH 0 = first instruction fetch following any program
transfer
1 = no program transfer
bit 14
bit 15 ch 62
ch 63 LOWBYTE
HIBYTE These are translation RAM signals which describe the
bus cycle.
15:14
0:0 use SIZ1, SIZ0 bits (status bits 6:5)
0:1 low-byte transfer
1:0 high-byte transfer
1:1 word transfer
Using the Emulation Analyzer
To position the trace display on screen
207