HP 54750A, User Manual, Page: 451 / 478

How the Instrument W orks
Standard and Enhanced T rigger Modes
Figure 13-19. 10 Gb/s digital eye diagram with a 1ms gating pulse.
Note the appearance of unexpected data points within the eye . These are the
result of false triggers on the gate enable rising edge .
Since the gating signal is completely asynchronous with the trigger signal, the
required condition for false triggers occurs frequently . The number of false
triggers can be reduced by synchronizing the gate enable rising edge with the
clock. If one could ensure that the gate enable would only be asserted when
the trigger input was low , no false triggers would occur . Figure 13-20 shows
the result of triggering the low speed gating pulse generator from the 10 Gb/s
pattern generator .
13-31