Rev. 1.10
128
November 04, 2019
Rev. 1.10
129
November 04, 2019
HT45F5Q-3
Battery Charger Flash MCU
HT45F5Q-3
Battery Charger Flash MCU
1. A UUSR register access
2. A UTXR_RXR register write execution
Note that both the UTXIF and UTIDLE bits are cleared by the same software sequence.
Transmit Break
If the UTXBRK bit is set then break characters will be sent on the next transmission. Break character
transmission consists of a start bit, followed by 13×N ‘0’ bits and stop bits, where N=1, 2, etc. If a
break character is to be transmitted then the UTXBRK bit must be first set by the application program,
and then cleared to generate the stop bits. Transmitting a break character will not generate a transmit
interrupt. Note that a break condition length is at least 13 bits long. If the UTXBRK bit is continually
kept at a logic high level then the transmitter circuitry will transmit continuous break characters. After
the application program has cleared the UTXBRK bit, the transmitter will finish transmitting the last
break character and subsequently send out one or two stop bits. The automatic logic highs at the end
of the last break character will ensure that the start bit of the next frame is recognized.
UART Receiver
The UART is capable of receiving word lengths of either 8 or 9 bits. If the UBNO bit is set, the word
length will be set to 9 bits with the MSB being stored in the URX8 bit of the UUCR1 register. At the
receiver core lies the Receive Serial Shift Register, commonly known as the RSR. The data which
is received on the RX external input pin is sent to the data recovery block. The data recovery block
operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the baud
rate. After the RX pin is sampled for the stop bit, the received data in RSR is transferred to the receive
data register, if the register is empty. The data which is received on the external RX input pin is sampled
three times by a majority detect circuit to determine the logic level that has been placed onto the RX pin.
It should be noted that the RSR register, unlike many other registers, is not directly mapped into the Data
Memory area and as such is not available to the application program for direct read/write operations.
Receiving Data
When the UART receiver is receiving data, the data is serially shifted in on the external RX input
pin, LSB first. In the read mode, the UTXR_RXR register forms a buffer between the internal bus
and the receiver shift register. The UTXR_RXR register is a two byte deep FIFO data buffer, where
two bytes can be held in the FIFO while a third byte can continue to be received. Note that the
application program must ensure that the data is read from UTXR_RXR before the third byte has
been completely shifted in, otherwise this third byte will be discarded and an overrun error UOERR
will be subsequently indicated. The steps to initiate a data transfer can be summarized as follows:
•
Make the correct selection of UBNO, UPRT and UPREN bits to define the word length, parity type.
•
Setup the UBRG register to select the desired baud rate.
•
Set the URXEN bit to ensure that the RX pin is used as a UART receiver pin.
At this point the receiver will be enabled which will begin to look for a start bit.
When a character is received the following sequence of events will occur:
•
The URXIF bit in the UUSR register will be set when the UTXR_RXR register has data
available. There will be at most one more character available before an overrun error occurs.
•
When the contents of the shift register have been transferred to the UTXR_RXR register, then if
the URIE bit is set, an interrupt will be generated.
•
If during reception, a frame error, noise error, parity error, or an overrun error has been detected,
then the error flags can be set.
The URXIF bit can be cleared using the following software sequence:
1. A UUSR register access
2. A UTXR_RXR register read execution
