Rev. 1.10
42
November 04, 2019
Rev. 1.10
43
November 04, 2019
HT45F5Q-3
Battery Charger Flash MCU
HT45F5Q-3
Battery Charger Flash MCU
Entering the IDLE0 Mode
There is only one way for the device to enter the IDLE0 Mode and that is to execute the “HALT”
instruction in the application program with the FHIDEN bit in the SCC register equal to “0” and the
FSIDEN bit in the SCC register equal to “1”. When this instruction is executed under the conditions
described above, the following will occur:
•
The f
H
clock will be stopped and the application program will stop at the “HALT” instruction, but
the f
SUB
clock will be on.
•
The Data Memory contents and registers will maintain their present condition.
•
The I/O ports will maintain their present conditions.
•
In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
•
The WDT will be cleared and resume counting if the WDT function is enabled. If the WDT
function is disabled, the WDT will be cleared and then stopped.
Entering the IDLE1 Mode
There is only one way for the device to enter the IDLE1 Mode and that is to execute the “HALT”
instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register
equal to “1”. When this instruction is executed under the conditions described above, the following
will occur:
•
The f
H
and f
SUB
clocks will be on but the application program will stop at the “HALT” instruction.
•
The Data Memory contents and registers will maintain their present condition.
•
The I/O ports will maintain their present conditions.
•
In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
•
The WDT will be cleared and resume counting if the WDT function is enabled. If the WDT
function is disabled, the WDT will be cleared and then stopped.
Entering the IDLE2 Mode
There is only one way for the device to enter the IDLE2 Mode and that is to execute the “HALT”
instruction in the application program with the FHIDEN bit in the SCC register equal to “1” and the
FSIDEN bit in the SCC register equal to “0”. When this instruction is executed under the conditions
described above, the following will occur:
•
The f
H
clock will be on but the f
SUB
clock will be off and the application program will stop at the
“HALT” instruction.
•
The Data Memory contents and registers will maintain their present condition.
•
The I/O ports will maintain their present conditions.
•
In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
•
The WDT will be cleared and resume counting if the WDT function is enabled. If the WDT
function is disabled, the WDT will be cleared and then stopped.
