Rev. 1.10
32
November 04, 2019
Rev. 1.10
33
November 04, 2019
HT45F5Q-3
Battery Charger Flash MCU
HT45F5Q-3
Battery Charger Flash MCU
Bit 5
EEREN
: Emulated EEPROM Erase enable
0: Disable
1: Enable
This bit is used to enable the Emulated EEPROM erase function and must be set high
before erase operations are carried out. This bit will be automatically reset to zero by
the hardware after the erase cycle has finished. Clearing this bit to zero will inhibit the
Emulated EEPROM erase operations.
Bit 4
EER
: Emulated EEPROM Erase control
0: Erase cycle has finished
1: Activate an erase cycle
When this bit is set high by the application program, an erase cycle will be activated. This
bit will be automatically reset to zero by the hardware after the erase cycle has finished.
Setting this bit high will have no effect if the EEREN has not first been set high.
Bit 3
EWREN
: Emulated EEPROM Write enable
0: Disable
1: Enable
This bit is used to enable the Emulated EEPROM write function and must be set high
before write operations are carried out. This bit will be automatically reset to zero by
the hardware after the write cycle has finished. Clearing this bit to zero will inhibit the
Emulated EEPROM write operations.
Bit 2
EWR
: Emulated EEPROM Write control
0: Write cycle has finished
1: Activate a write cycle
When this bit is set high by the application program, a write cycle will be activated. This
bit will be automatically reset to zero by the hardware after the write cycle has finished.
Setting this bit high will have no effect if the EWREN has not first been set high.
Bit 1
ERDEN
: Emulated EEPROM Read enable
0: Disable
1: Enable
This bit is used to enable the Emulated EEPROM read function and must be set
high before read operations are carried out. Clearing this bit to zero will inhibit the
Emulated EEPROM read operations.
Bit 0
ERD
: Emulated EEPROM Read control
0: Read cycle has finished
1: Activate a read cycle
When this bit is set high by the application program, a read cycle will be activated. This
bit will be automatically reset to zero by the hardware after the read cycle has finished.
Setting this bit high will have no effect if the ERDEN has not first been set high.
Note:
1. The EEREN, EER, EWREN, EWR, ERDEN and ERD cannot be set to “1” at the same time
in one instruction.
2. Note that the CPU will be stopped when a read, write or erase operation is successfully
activated.
3. Ensure that the f
SYS
clock frequency is equal to or greater than 2MHz and the f
SUB
clock is
stable before executing the erase or write operation.
4. Ensure that the read, write or erase operation is totally complete before executing other
operations.
