Rev. 1.10
80
November 04, 2019
Rev. 1.10
81
November 04, 2019
HT45F5Q-3
Battery Charger Flash MCU
HT45F5Q-3
Battery Charger Flash MCU
Timer/Counter Mode
To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 11 respectively.
The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode
generating the same interrupt flags. The exception is that in the Timer/Counter Mode the STM
output pin is not used. Therefore the above description and Timing Diagrams for the Compare
Match Output Mode can be used to understand its function. As the STM output pin is not used in
this mode, the pin can be used as a normal I/O pin or other pin-shared function.
PWM Output Mode
To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 10 respectively
and also the STIO1 and STIO0 bits should be set to 10 respectively. The PWM function within
the STM is useful for applications which require functions such as motor control, heating control,
illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the
STM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS
values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM Output Mode, the STCCLR bit has no effect as the
PWM period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one
register is used to clear the internal counter and thus control the PWM waveform frequency, while
the other one is used to control the duty cycle. Which register is used to control either frequency
or duty cycle is determined using the STDPX bit in the STMC1 register. The PWM waveform
frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers.
An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match
occurs from either Comparator A or Comparator P. The STOC bit in the STMC1 register is used to
select the required polarity of the PWM waveform while the two STIO1 and STIO0 bits are used to
enable the PWM output or to force the STM output pin to a fixed high or low level. The STPOL bit
is used to reverse the polarity of the PWM output waveform.
• 10-bit STM, PWM Output Mode, Edge-aligned Mode, STDPX=0
CCRP
001b
010b
011b
100b
101b
110b
111b
000b
Period
128
256
384
512
640
768
896
1024
Duty
CCRA
If f
SYS
=8MHz, TM clock source is f
SYS
/4, CCRP=100b and CCRA=128,
The STM PWM output frequency=(f
SYS
/4)/512=f
SYS
/2048=4kHz, duty=128/512=25%.
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.
• 10-bit STM, PWM Output Mode, Edge-aligned Mode, STDPX=1
CCRP
001b
010b
011b
100b
101b
110b
111b
000b
Period
CCRA
Duty
128
256
384
512
640
768
896
1024
The PWM output period is determined by the CCRA register value together with the STM clock
while the PWM duty cycle is defined by the CCRP register value.
