Holtek HT45F5Q-3 Manual Download

Page: 106 / 163

Rev. 1.10

106

November 04, 2019

Rev. 1.10

107

November 04, 2019

HT45F5Q-3

Battery Charger Flash MCU

HT45F5Q-3

Battery Charger Flash MCU

Clear WCOL

Write Data

into SIMD

WCOL=1?

Transmission

completed?

(TRF=1?)

Read Data

from SIMD

Clear TRF

END

Transfer

finished?

SPI Transfer

Master or Slave

SIMEN=1

Configure CKPOLB,

CKEG, CSEN and MLS

SIM[2:0]=000, 001,

010, 011 or 100

SIM[2:0]=101

Master

Slave

UMD=0

SPI Transfer Control Flowchart

Summary of Contents for HT45F5Q-3

Page 1: ...Battery Charger Flash MCU HT45F5Q 3 Revision V1 10 Date November 04 2019...

Page 2: ...ting Frequency Characteristic Curves 13 System Start Up Time Characteristics 14 Input Output Characteristics 14 Memory Characteristics 15 LVR Electrical Characteristics 15 A D Converter Electrical Cha...

Page 3: ...ata from the Emulated EEPROM 33 Programming Considerations 33 Oscillators 35 Oscillator Overview 35 System Clock Configurations 35 Internal High Speed RC Oscillator HIRC 36 Internal 32kHz Oscillator L...

Page 4: ...8 A D Converter Register Description 89 A D Converter Data Registers SADOL SADOH 89 A D Converter Reference Voltage 91 A D Converter Input Signal 91 A D Converter Operation 92 Conversion Rate and Timi...

Page 5: ...Application Descriptions 145 Introduction 145 Functional Description 145 Hardware Circuit 146 Instruction Set 147 Introduction 147 Instruction Timing 147 Moving and Transferring Data 147 Arithmetic O...

Page 6: ...eatures Flash Program Memory 4K 15 RAM Data Memory 256 8 Emulated EEPROM Memory 32 15 Watchdog Timer function 23 bidirectional I O lines Two pin shared external interrupts Multiple Timer Modules for t...

Page 7: ...current closed loop charging control The device therefore reduces the need for the usually required external TL431 component operational amplifier and resistance analogic D A Converter in traditional...

Page 8: ...32kHz USIM Clock System MUX HIRC 8MHz Stack 6 level RAM 256 8 ROM 4K 15 Emulated EEPROM 32 15 Watchdog Timer LVR MUX 12 bit ADC 12 bit DAC 14 bit DAC Battery Charge Module Digital Peripherals Time Ba...

Page 9: ...s Refer to the Standby Current Considerations and Input Output Ports sections Pin Description The function of each pin is listed in the following table however the details behind how each pin is confi...

Page 10: ...PAS1 CMOS SPI serial data output TX PAS1 CMOS UART TX serial data output PB0 AN0 PB0 PBPU PBS0 ST CMOS General purpose I O Register enabled pull up AN0 PBS0 AN A D Converter external input 0 PB1 AN1...

Page 11: ...ta input PC3 SCOM0 SCK SCL PC3 PCPU PCS0 ST CMOS General purpose I O Register enabled pull up SCOM0 PCS0 AN Software LCD COM output SCK PCS0 IFS ST CMOS SPI serial clock SCL PCS0 IFS ST NMOS I2 C cloc...

Page 12: ...cteristics Ta 40 C 105 C Symbol Operating Mode Test Conditions Min Typ Max Unit VDD Conditions IDD SLOW Mode LIRC 5V fSYS 32kHz OPA0 1 enable 0 6 1 2 mA FAST Mode HIRC 5V fSYS 8MHz OPA0 1 enable 2 2 3...

Page 13: ...trimmed by the writer 2 The row below the 3V 5V trim voltage row is provided to show the values for the full VDD range operating voltage It is recommended that the trim voltage is fixed at 3V for appl...

Page 14: ...e frequency tables For example tHIRC 1 fHIRC tSYS 1 fSYS etc 3 If the LIRC is used as the system clock and if it is off when in the SLEEP Mode then an additional LIRC start up time tSTART as provided...

Page 15: ...ion can only be executed when the fSYS clock frequency is equal to or greater than 2MHz LVR Electrical Characteristics Ta 40 C 105 C unless otherwise specified Symbol Parameter Test Conditions Min Typ...

Page 16: ...ent for D A Converter 0 Enable 5V 600 800 A Additional Current for D A Converter 1 Enable 5V 500 600 A tST D A Converter Settling Time 5V CLOAD 50pF 5 s DNL D A Converter 0 Differential Non linearity...

Page 17: ...39 5V 35 50 65 3V ISEL 1 0 10B 42 60 78 5V 70 100 130 3V ISEL 1 0 11B 82 6 118 0 153 4 5V 140 200 260 VSCOM VDD 2 Voltage for LCD COM Ports 2 2V 5 5V No load 0 475 VDD 0 500 VDD 0 525 VDD V Power on R...

Page 18: ...ns Clocking and Pipelining The main system clock derived from either an HIRC or LIRC oscillator is subdivided into four internally generated non overlapping clocks T1 T4 The Program Counter is increme...

Page 19: ...sferring data directly into this register a short program jump can be executed directly however as only this low byte is available for manipulation the jumps are limited to the present page of memory...

Page 20: ...functions Arithmetic operations ADD ADDM ADC ADCM SUB SUBM SBC SBCM DAA Logic operations AND OR XOR ANDM ORM XORM CPL CPLA Rotation RRA RR RRCA RRC RLA RL RLCA RLC Increment and Decrement INCA INC DEC...

Page 21: ...te from the Program Memory will be transferred to the user defined Data Memory register m as specified in the instruction The higher order table data byte from the Program Memory will be transferred t...

Page 22: ...se high table pointer mov tbhp a it is not necessary to set tbhp if executing tabrdl tabrd tempreg1 transfers value in table referenced by table pointer data at program memory address 0F06H transferre...

Page 23: ...which is used to emulate the HT45F5Q 3 device This EV chip device also provides an On Chip Debug function to debug the real MCU device during the development process The EV chip and the real MCU devi...

Page 24: ...ferent Data Memory banks is achieved by setting the Bank Pointer to the correct value The address range of the Special Purpose Data Memory for the device is from 00H to 7FH in Bank 0 while the General...

Page 25: ...H 43H 44H 45H 46H 47H 4EH 50H 51H 52H 59H 58H 7FH 53H 54H 55H 56H 57H 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 19H 18H 1BH 1AH 1DH 1CH 1FH 13H 14H 15H 16H 17H 1EH 20...

Page 26: ...ters MP0 MP1 Two Memory Pointers known as MP0 and MP1 are provided These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers provid...

Page 27: ...in higher programming and timing overheads Data transfer operations usually involve the temporary storage function of the Accumulator for example when transferring data between one user defined regist...

Page 28: ...h nibble into the low nibble in subtraction otherwise AC is cleared Z is set if the result of an arithmetic or logical operation is zero otherwise Z is cleared OV is set if an operation results in a c...

Page 29: ...lity of the Emulated EEPROM storage allows information such as product identification numbers calibration values specific user data system setup data or other product information to be stored directly...

Page 30: ...EEREN EER EWREN EWR ERDEN ERD Emulated EEPROM Register List EAR Register Bit 7 6 5 4 3 2 1 0 Name EAR4 EAR3 EAR2 EAR1 EAR0 R W R W R W R W R W R W POR 0 0 0 0 0 Bit 7 5 Unimplemented read as 0 Bit 4 0...

Page 31: ...R W R W R W POR 0 0 0 0 0 0 0 Bit 7 Unimplemented read as 0 Bit 6 0 D14 D8 The third Emulated EEPROM data bit 14 bit 8 ED3L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R...

Page 32: ...l 0 Write cycle has finished 1 Activate a write cycle When this bit is set high by the application program a write cycle will be activated This bit will be automatically reset to zero by the hardware...

Page 33: ...e the write function After this the EWR bit in the ECR register must be immediately set high to initiate a write cycle These two instructions must be executed in two consecutive instruction cycles to...

Page 34: ...80H for 8ms C0H for 16ms MOV ECR A CLR EMI SET EEREN set EEREN bit enable erase operation SET EER start Erase Cycle set EER bit executed immediately after setting EEREN bit SET EMI BACK SZ EER check...

Page 35: ...In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupts Two fully integrated internal oscillators requiring...

Page 36: ...have high performance but often still demand that they consume as little power as possible conflicting requirements that are especially true in battery powered portable applications The fast clocks re...

Page 37: ...ne with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application There are two modes allowing normal operation of the mic...

Page 38: ...al function will also be stopped too However the fLIRC clock can continues to operate if the WDT function is enabled IDLE0 Mode The IDLE0 Mode is entered when a HALT instruction is executed and when t...

Page 39: ...able This bit is used to control whether the high speed oscillator is activated or stopped when the CPU is switched off by executing an HALT instruction Bit 0 FSIDEN Low Frequency oscillator control w...

Page 40: ...using the CKS2 CKS0 bits in the SCC register while Mode Switching from the FAST SLOW Modes to the SLEEP IDLE Modes is executed via the HALT instruction When a HALT instruction is executed whether the...

Page 41: ...ich will consume less power Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption The SLOW Mode is sourced from the LIR...

Page 42: ...ion is executed IDLE1 Mode FHIDEN 1 FSIDEN 1 HALT instruction is executed IDLE2 Mode FHIDEN 1 FSIDEN 0 HALT instruction is executed Entering the SLEEP Mode There is only one way for the device to ente...

Page 43: ...conditions described above the following will occur The fH and fSUB clocks will be on but the application program will stop at the HALT instruction The Data Memory contents and registers will maintai...

Page 44: ...the device is woken up again it will take a considerable time for the original system oscillator to restart stabilise and allow normal operation to resume After the system enters the SLEEP or IDLE Mod...

Page 45: ...enable disable and reset MCU operation WDTC Register Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R W R W R W R W R W R W R W R W R W POR 0 1 0 1 0 0 1 1 Bit 7 3 WE4 WE0 WDT function soft...

Page 46: ...nd 10101B it will reset the device after a delay time tSRESET After power on these bits will have a value of 01010B WE4 WE0 Bits WDT Function 10101B Disable 01010B Enable Any other value Reset MCU Wat...

Page 47: ...ess a power on reset also ensures that certain other registers are preset to known conditions All the I O port and port control registers will power up in a high condition ensuring that all pins will...

Page 48: ...eeps more than a tLVR time In this situation the register contents will remain the same after such a reset occurs Any register value other than 01011010B and 10100101B will also result in the generati...

Page 49: ...ster and are controlled by various microcontroller operations such as the SLEEP or IDLE Mode function or Watchdog Timer The reset flags are shown in the table TO PDF RESET Conditions 0 0 Power on rese...

Page 50: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PAWU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u IECC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PB...

Page 51: ...0 0 0 0 0 u u u u SIMC0 111 0 0 0 0 0 111 0 0 0 0 0 111 0 0 0 0 0 u u u u u u u u SIMC1 UMD 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 u u u u u u u u UUCR1 UMD 1 0 0 0 0 0 0 x 0 0 0 0 0 0 0 x...

Page 52: ...WU3 PAWU2 PAWU1 PAWU0 PB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PBC PBC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 PBPU PBPU7 PBPU6 PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0 PC PC6 PC5 PC4 PC3 PC2 PC1 PC0 PCC PCC6 PCC5 P...

Page 53: ...ports is directly mapped to a bit in its associated port control register For the I O pin to function as an input the corresponding bit of the control register must be written as a 1 This will then a...

Page 54: ...pins such as INT0 CTCK etc which share the same pin shared control configuration with their corresponding general purpose I O functions when setting the relevant pin shared control bit fields To selec...

Page 55: ...lection 00 PA5 01 CTPB 10 OPA0P 11 PA5 Bit 1 0 PAS11 PAS10 PA4 Pin Shared function selection 00 PA4 STCK 01 STP 10 SDI SDA RX 11 PA4 STCK PBS0 Register Bit 7 6 5 4 3 2 1 0 Name PBS07 PBS06 PBS05 PBS04...

Page 56: ...ed function selection 00 PB5 01 PB5 10 PB5 11 AN5 Bit 1 0 PBS11 PBS10 PB4 Pin Shared function selection 00 PB4 01 PB4 10 PB4 11 AN4 PCS0 Register Bit 7 6 5 4 3 2 1 0 Name PCS07 PCS06 PCS05 PCS04 PCS03...

Page 57: ...01 SCOM3 10 PC6 11 PC6 Bit 3 2 PCS13 PCS12 PC5 Pin Shared function selection 00 PC5 01 SCOM2 10 PC5 11 PC5 Bit 1 0 PCS11 PCS10 PC4 Pin Shared function selection 00 PC4 01 SCOM1 10 SCS 11 PC4 IFS Regi...

Page 58: ...he output data from the data latch or I O pin which is specially designed for the IEC60730 self diagnostic test on the I O function and A D paths There is a register IECC which is used to control the...

Page 59: ...converting the corresponding digital data without any external analog input voltage connected READ PORT function enabled AN0 Pin shared path switched on automatically External analog input channel se...

Page 60: ...main features and differences between the two types of TMs are summarised in the accompanying table Function CTM STM Timer Counter Input Capture Compare Match Output PWM Output Single Pulse Output PWM...

Page 61: ...igger input pin in single pulse output mode The other STM input pin STPI is the capture input whose active edge can be a rising edge a falling edge or both rising and falling edges and the active edge...

Page 62: ...to access the CCRA low byte registers named xTMAL using the following access procedures Accessing the CCRA low byte register without following these access procedures will result in unpredictable val...

Page 63: ...ames Comparator A and Comparator P These comparators will compare the value in the counter with CCRP and CCRA registers The CCRP comparator is 3 bit wide whose value is compared with the highest 3 bit...

Page 64: ...YS 010 fH 16 011 fH 64 100 fSUB 101 fSUB 110 CTCK rising edge clock 111 CTCK falling edge clock These three bits are used to select the clock source for the CTM The external pin clock source can be ch...

Page 65: ...Output Mode 01 Undefined 10 PWM Output Mode 11 Timer Counter Mode These bits setup the required operating mode for the CTM To ensure reliable operation the CTM should be switched off before any change...

Page 66: ...ut Mode it determines if the PWM signal is active high or active low Bit 2 CTPOL CTM CTP Output polarity control 0 Non invert 1 Invert This bit controls the polarity of the CTP output pin When the bit...

Page 67: ...eared by three methods These are a counter overflow a compare match from Comparator A and a compare match from Comparator P When the CTCCLR bit is low there are two ways in which the counter can be cl...

Page 68: ...re zero then no pin change will take place Counter Value 0x3FF CCRP CCRA CTON CTPAU CTPOL CCRP Int Flag CTMPF CCRA Int Flag CTMAF CTM O P Pin Time CCRP 0 CCRP 0 Counter overflow CCRP 0 Counter cleared...

Page 69: ...t affected by CTMAF flag Remains High until reset by CTON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when CTPOL is high CTMPF not generated No...

Page 70: ...lear the internal counter and thus control the PWM waveform frequency while the other one is used to control the duty cycle Which register is used to control either frequency or duty cycle is determin...

Page 71: ...cle set by CCRA PWM resumes operation Output controlled by other pin shared function Output Inverts when CTPOL 1 PWM Period set by CCRP CTM O P Pin CTOC 0 CCRA Int Flag CTMAF CCRP Int Flag CTMPF CTDPX...

Page 72: ...ter Reset when CTON returns high PWM Duty Cycle set by CCRP PWM resumes operation Output controlled by other pin shared function Output Inverts when CTPOL 1 PWM Period set by CCRA CTM O P Pin CTOC 0 C...

Page 73: ...rnal comparators with the names Comparator A and Comparator P These comparators will compare the value in the counter with CCRP and CCRA registers The CCRP comparator is 3 bit wide whose value is comp...

Page 74: ...011 fH 64 100 fSUB 101 fSUB 110 STCK rising edge clock 111 STCK falling edge clock These three bits are used to select the clock source for the STM The external pin clock source can be chosen to be ac...

Page 75: ...STM0 STIO1 STIO0 STOC STPOL STDPX STCCLR R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 STM1 STM0 Select STM Operating Mode 00 Compare Match Output Mode 01 Capture Input Mode 10 PWM O...

Page 76: ...ion depends upon whether STM is being used in the Compare Match Output Mode or in the PWM Output Mode Single Pulse Output Mode It has no effect if the STM is in the Timer Counter Mode In the Compare M...

Page 77: ...POR 0 0 Bit 7 2 Unimplemented read as 0 Bit 1 0 D9 D8 STM Counter High Byte Register bit 1 bit 0 STM 10 bit Counter bit 9 bit 8 STMAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W...

Page 78: ...ly the STMAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers Therefore when STCCLR is high no STMPF interrupt request flag will be g...

Page 79: ...OC 0 Output Toggle with STMAF flag Note STIO 1 0 10 Active High Output select Here STIO 1 0 11 Toggle Output select Output not affected by STMAF flag Remains High until reset by STON bit Output Pin Re...

Page 80: ...utput select Here STIO 1 0 11 Toggle Output select Output not affected by STMAF flag Remains High until reset by STON bit Output Pin Reset to Initial value Output controlled by other pin shared functi...

Page 81: ...o generate the PWM waveform one register is used to clear the internal counter and thus control the PWM waveform frequency while the other one is used to control the duty cycle Which register is used...

Page 82: ...Reset when STON returns high STDPX 0 STM 1 0 10 PWM Duty Cycle set by CCRA PWM resumes operation Output controlled by other pin shared function Output Inverts when STPOL 1 PWM Period set by CCRP STM O...

Page 83: ...ter Reset when STON returns high STDPX 1 STM 1 0 10 PWM Duty Cycle set by CCRP PWM resumes operation Output controlled by other pin shared function Output Inverts when STPOL 1 PWM Period set by CCRA S...

Page 84: ...ng edge will be generated The STON bit should remain high when the pulse is in its active state The generated pulse trailing edge will be generated when the STON bit is cleared to zero which can be im...

Page 85: ...tput Inverts when STPOL 1 No CCRP Interrupts generated STM O P Pin STOC 0 STCK pin Software Trigger Cleared by CCRA match STCK pin Trigger Auto set by STCK pin Software Trigger Software Clear Software...

Page 86: ...n the counter will continue to free run until the STON bit changes from high to low When a CCRP compare match occurs the counter will reset back to zero in this way the CCRP value can be used to contr...

Page 87: ...O 1 0 Value XX YY XX YY Active edge Active edge Active edge 00 Rising edge 01 Falling edge 10 Both edges 11 Disable Capture Capture Input Mode Note 1 STM 1 0 01 and active edge set by the STIO 1 0 bit...

Page 88: ...tage 20 A2P and convert these signals directly into a 12 bit digital value The external or internal analog signal to be converted is determined by the SAINS2 SAINS0 bits together with the SACS3 SACS0...

Page 89: ...ntents will be unchanged if the A D converter is disabled ADRFS SADOH SADOL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1...

Page 90: ...e to enable the A D converter If the bit is set low then the A D converter will be switched off reducing the device power consumption When the A D converter function is disabled the contents of the A...

Page 91: ...VREF The desired selection is made using the SAVRS1 and SAVRS0 bits When the SAVRS bit field is set to 01 the A D converter reference voltage will come from the VDD Otherwise if the SAVRS bit field is...

Page 92: ...rrupts are enabled an appropriate internal interrupt signal will be generated This A D internal interrupt signal will direct the program flow to the associated A D internal interrupt address for proce...

Page 93: ...ed in an analog to digital conversion process and its associated timing After an A D conversion process has been initiated by the application program the microcontroller internal hardware will begin t...

Page 94: ...The A D conversion procedure can now be initialized by setting the START bit from low to high and then low again Step 10 If A D conversion is in progress the ADBZ flag will be set high After the A D...

Page 95: ...d of polling the ADBZ bit in the SADC0 register is used to detect when the conversion cycle is complete whereas in the second example the A D interrupt is used to determine when the conversion is comp...

Page 96: ...nitiate conversion set START reset A D clr START start A D clr ADF clear ADC interrupt request flag set ADE enable A D converter interrupt set EMI enable global interrupt ADC interrupt service routine...

Page 97: ...e Module Structure Note 1 The OPA0 and OPA1 are always enabled while the OPA2 is controlled by the OP2EN bit in DAOPC register 2 The OPA0 and OPA1 are open drain outputs 3 The OPA0 and OPA1 do not nee...

Page 98: ...t 7 6 5 4 3 2 1 0 Name D13 D12 D11 D10 D9 D8 R W R W R W R W R W R W R W POR 0 0 0 0 0 0 Bit 7 6 Unimplemented read as 0 Bit 5 0 D13 D8 D A converter 0 output control code high byte The D A converter...

Page 99: ...A2 enable disable and output status monitoring The OPVOS register is used for OPA2 input offset calibration voltage selection and control OPVOS Register Bit 7 6 5 4 3 2 1 0 Name OOFM OOF5 OOF4 OOF3 OO...

Page 100: ...f whether the UART SPI or I2 C type is used is made using the UART mode selection bit named UMD and the SPI I2 C operating mode control bits named SIM2 SIM0 in the SIMC0 register These pull high resis...

Page 101: ...he device is in the master or slave mode and upon the condition of certain control bits such as CSEN and SIMEN SIMD TX RX Shift Register SDI Pin Clock Edge Polarity Control CKEG CKPOLB Clock Source Se...

Page 102: ...EB0 SIMEN SIMICF R W R W R W R W R W R W R W R W R W POR 1 1 1 0 0 0 0 0 Bit 7 5 SIM2 SIM0 USIM SPI I2 C Operating Mode Control 000 SPI master mode SPI clock is fSYS 4 001 SPI master mode SPI clock is...

Page 103: ...completely finished the SIMICF bit will be set to 1 together with the TRF bit When this condition occurs the corresponding interrupt will occur if the interrupt function is enabled However the TRF bi...

Page 104: ...bit is the Transmit Receive Complete flag and is set 1 automatically when an SPI data transmission is completed but must set to 0 by the application program It can be used to generate an interrupt SPI...

Page 105: ...D4 D2 D5 D1 D6 D0 D7 SPI Master Mode Timing SCK CKPOLB 1 SCK CKPOLB 0 SCS SDO SDI Data Capture Write to SIMD SDO does not change until first SCK edge D7 D0 D6 D1 D5 D2 D4 D3 D3 D4 D2 D5 D1 D6 D0 D7 SP...

Page 106: ...Data into SIMD WCOL 1 Transmission completed TRF 1 Read Data from SIMD Clear TRF END Transfer finished A SPI Transfer Master or Slave SIMEN 1 Configure CKPOLB CKEG CSEN and MLS A SIM 2 0 000 001 010 0...

Page 107: ...B in the SIMC2 register If in Slave Mode the SCK line will be in a floating condition If the SIMEN bit is low then the bus will be disabled and SCS SDI SDO and SCK will all become I O pins or the othe...

Page 108: ...to zero then go to the following step Step 6 Check the TRF bit or wait for a USIM SPI serial bus interrupt Step 7 Read data from the SIMD register Step 8 Clear TRF Step 9 Go to step 4 Error Detection...

Page 109: ...ontrol of the bus For the device which only operates in slave mode there are two methods of transferring data on the I2 C bus the slave transmit mode and the slave receive mode The pull high control f...

Page 110: ...roperly configuring the UMD and SIM2 SIM0 bits in the SIMC0 register Register Name Bit 7 6 5 4 3 2 1 0 SIMC0 SIM2 SIM1 SIM0 UMD SIMDEB1 SIMDEB0 SIMEN SIMICF SIMC1 HCF HAAS HBB HTX TXAK SRW IAMWU RXAK...

Page 111: ...ster mode SPI clock is fSYS 16 010 SPI master mode SPI clock is fSYS 64 011 SPI master mode SPI clock is fSUB 100 SPI master mode SPI clock is CTM CCRP match frequency 2 101 SPI slave mode 110 I2 C sl...

Page 112: ...ster Bit 7 6 5 4 3 2 1 0 Name HCF HAAS HBB HTX TXAK SRW IAMWU RXAK R W R R R R W R W R R W R POR 1 0 0 0 0 0 0 1 Bit 7 HCF I2 C Bus data transfer completion flag 0 Data is being transferred 1 Completi...

Page 113: ...e The slave transmitter will therefore continue sending out data until the RXAK flag is 1 When this occurs the slave transmitter will release the SDA line to allow the master to send a STOP signal to...

Page 114: ...ed The next bit following the address which is the 8th bit defines the read write status and will be saved to the SRW bit of the SIMC1 register The slave device will then transmit an acknowledge bit w...

Page 115: ...vel 0 before it can receive the next data byte If the slave transmitter does not receive an acknowledge bit signal from the master receiver then the slave transmitter will release the SDA line to allo...

Page 116: ...ception of erroneous clock sources a time out function is provided If the clock source to the I2 C is not received for a while then the I2 C circuitry and registers will be reset after a certain time...

Page 117: ...sable 1 Enable Bit 6 SIMTOF USIM I2 C Time out flag 0 No time out occurred 1 Time out occurred This bit is set high when time out occurs and can only be cleared by application program Bit 5 0 SIMTOS5...

Page 118: ...on is disabled by clearing the UMD UREN UTXEN or URXEN bit the TX or RX pin will be set to a floating state At this time whether the internal pull high resistor is connected to the TX or RX pin or not...

Page 119: ...UPREN UPRT USTOPS UTXBRK URX8 UTX8 UUCR2 UTXEN URXEN UBRGH UADDEN UWAKE URIE UTIIE UTEIE UTXR_RXR UTXRX7 UTXRX6 UTXRX5 UTXRX4 UTXRX3 UTXRX2 UTXRX1 UTXRX0 UBRG UBRG7 UBRG6 UBRG5 UBRG4 UBRG3 UBRG2 UBRG...

Page 120: ...d by an access to the UTXR_RXR data register Bit 5 UFERR Framing error flag 0 No framing error is detected 1 Framing error is detected The UFERR flag is the framing error flag When this read only flag...

Page 121: ...flag is not generated when a data character or a break is queued and ready to be sent Bit 0 UTXIF Transmit UTXR_RXR data register status 0 Character is not transferred to the transmit shift register 1...

Page 122: ...will be disabled Bit 4 UPRT Parity type selection bit 0 Even parity for parity generator 1 Odd parity for parity generator This bit is the parity type selection bit When this bit is equal to 1 odd pa...

Page 123: ...be disabled with any pending data receptions being aborted In addition the receive buffers will be reset In this situation the RX pin will be set in a floating state If the URXEN bit is equal to 1 and...

Page 124: ...MF will be set If this bit is equal to 0 the USIM interrupt request flag USIMF will not be influenced by the condition of the UOERR or URXIF flags Bit 1 UTIIE Transmitter Idle interrupt enable control...

Page 125: ...in the UBRG register the required baud rate can be setup Note that because the actual baud rate is determined using a discrete value N placed in the UBRG register there will be an error associated be...

Page 126: ...diately suspended and the UART will be reset to a condition as defined above If the UART is then subsequently re enabled it will restart again in the same configuration Data Parity and Stop Bit Select...

Page 127: ...When the UART is transmitting data the data is shifted on the TX pin from the shift register with the least significant bit first In the transmit mode the UTXR_RXR register forms a buffer between the...

Page 128: ...received on the external RX input pin is sampled three times by a majority detect circuit to determine the logic level that has been placed onto the RX pin It should be noted that the RSR register unl...

Page 129: ...URXIF flags will possibly be set Idle Status When the receiver is reading data which means it will be in between the detection of a start bit and the reading of a stop bit the receiver status flag in...

Page 130: ...a register empty transmitter idle receiver data available receiver overrun address detect and an RX pin wake up When any of these conditions are created if the global interrupt enable bit and the USIM...

Page 131: ...pt enable bits must also be enabled for correct interrupt generation This highest address bit is the 9th bit if UBNO 1 or the 8th bit if UBNO 0 If this bit is high then the received word will be defin...

Page 132: ...er a wake up before normal microcontroller resumes the USIM interrupt will not be generated until after this time has elapsed Software Controlled LCD Driver The device has the capability of driving ex...

Page 133: ...data correctness A CRC calculation takes a data stream or a block of data as its input and generates a 16 bit output remainder Ordinarily a data stream is suffixed by a CRC code and used as a checksum...

Page 134: ...h byte data register CRC Operation The CRC generator provides the 16 bit CRC result calculation based on the CRC16 and CCITT CRC16 polynomials In this CRC generator there are only these two polynomial...

Page 135: ...1 0000H 8005H 800FH 000AH 801BH 001EH 0014H 8011H Note The initial value of the CRC checksum register pair CRCDH and CRCDL is zero before each CRC input data is written into the CRCIN register Write 4...

Page 136: ...the accompanying table The number of registers falls into three categories The first is the INTC0 INTC2 registers which setup the primary interrupts the second is the MFI0 MFI1 register which setups...

Page 137: ...Rising and falling edges INTC0 Register Bit 7 6 5 4 3 2 1 0 Name TB0F INT1F INT0F TB0E INT1E INT0E EMI R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 Bit 7 Unimplemented read as 0 Bit 6 TB0F Time B...

Page 138: ...request 1 Interrupt request Bit 4 TB1F Time Base 1 interrupt request flag 0 No request 1 Interrupt request Bit 3 ADE A D Converter interrupt control 0 Disable 1 Enable Bit 2 MF1E Multi function 1 inte...

Page 139: ...request Bit 4 STMPF STM Comparator P match interrupt request flag 0 No request 1 Interrupt request Bit 3 2 Unimplemented read as 0 Bit 1 STMAE STM Comparator A match interrupt control 0 Disable 1 Enab...

Page 140: ...nesting from occurring However if other interrupt requests occur during this interval although the interrupt will not be immediately serviced the request flag will still be recorded If an interrupt r...

Page 141: ...pin is used as an external interrupt input The INTEG register is used to select the type of active edge that will trigger the external interrupt A choice of either rising or falling or both edge type...

Page 142: ...B0ON Time Base 0 Control 0 Disable 1 Enable Bit 6 3 Unimplemented read as 0 Bit 2 0 TB02 TB00 Select Time Base 0 Time out Period 000 20 fPSC 001 21 fPSC 010 22 fPSC 011 23 fPSC 100 24 fPSC 101 25 fPSC...

Page 143: ...ituation happens To allow the program to branch to its respective interrupt vector address the global interrupt enable bit EMI respective TM Interrupt enable bit and relevant Multi function Interrupt...

Page 144: ...rupt wake up function Programming Considerations By disabling the relevant interrupt enable bits a requested interrupt can be prevented from being serviced however once an interrupt request flag is se...

Page 145: ...urrent signal thus increasing the current resolution and reducing the detecting resistance power consumption The constant voltage mode constant current mode and constant current and constant voltage r...

Page 146: ...the internal 14 12 bit D A Converter resolution is not high enough the OPA0 and OPA1 positive terminals can be supplied by an external divider resistor to increase the voltage and current resolution H...

Page 147: ...le to implement As instructions which change the contents of the PCL will imply a direct jump to that new address one more cycle will be required Examples of such instructions would be CLR PCL or MOV...

Page 148: ...nstructions are the conditional branches Here a decision is first made regarding the condition of a certain data memory or individual bits Depending upon the conditions the program will continue with...

Page 149: ...Z C AC OV DAA m Decimal adjust ACC for Addition with result in Data Memory 1Note C Logic Operation AND A m Logical AND Data Memory to ACC 1 Z OR A m Logical OR Data Memory to ACC 1 Z XOR A m Logical...

Page 150: ...x Return from subroutine and load immediate data to ACC 2 None RETI Return from interrupt 2 None Table Read Operation TABRD m Read table specific page or current page to TBLH and Data Memory 2Note Non...

Page 151: ...and the specified immediate data are added The result is stored in the Accumulator Operation ACC ACC x Affected flag s OV Z AC C ADDM A m Add ACC to Data Memory Description The contents of the specif...

Page 152: ...F flags and the WDT are all cleared Operation WDT cleared TO 0 PDF 0 Affected flag s TO PDF CLR WDT1 Pre clear Watchdog Timer Description The TO PDF flags and the WDT are all cleared Note that this in...

Page 153: ...instruction which indicates that if the original BCD sum is greater than 100 it allows multiple precision decimal addition Operation m ACC 00H or m ACC 06H or m ACC 60H or m ACC 66H Affected flag s C...

Page 154: ...CC Affected flag s None NOP No operation Description No operation is performed Execution continues with the next instruction Operation No operation Affected flag s None OR A m Logical OR Data Memory t...

Page 155: ...mory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0 The rotated result is stored in the Accumulator and the conte...

Page 156: ...Data Memory from ACC with Carry Description The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator The result is stored in the Accumulator...

Page 157: ...ogram proceeds with the following instruction Operation m m 1 Skip if m 0 Affected flag s None SIZA m Skip if increment Data Memory is zero with result in ACC Description The contents of the specified...

Page 158: ...nterchanged The result is stored in the Accumulator The contents of the Data Memory remain unchanged Operation ACC 3 ACC 0 m 7 m 4 ACC 7 ACC 4 m 3 m 0 Affected flag s None SZ m Skip if Data Memory is...

Page 159: ...e high byte moved to TBLH Operation m program code low byte TBLH program code high byte Affected flag s None XOR A m Logical XOR Data Memory to ACC Description Data in the Accumulator and the specifie...

Page 160: ...ervals users are reminded to consult the Holtek website for the latest version of the Package Carton Information Additional supplementary information with regard to packaging is listed below Click on...

Page 161: ...ons Symbol Dimensions in inch Min Nom Max A 0 236 BSC B 0 154 BSC C 0 008 0 012 C 0 341 BSC D 0 069 E 0 025 BSC F 0 004 0 010 G 0 016 0 050 H 0 004 0 010 0 8 Symbol Dimensions in mm Min Nom Max A 6 00...

Page 162: ...nsions Symbol Dimensions in inch Min Nom Max A 0 236 BSC B 0 154 BSC C 0 008 0 012 C 0 390 BSC D 0 069 E 0 025 BSC F 0 004 0 010 G 0 016 0 050 H 0 004 0 010 0 8 Symbol Dimensions in mm Min Nom Max A 6...

Page 163: ...solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification nor recommends the use of its products for a...

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