Rev. 1.10
64
November 04, 2019
Rev. 1.10
65
November 04, 2019
HT45F5Q-3
Battery Charger Flash MCU
HT45F5Q-3
Battery Charger Flash MCU
Bit 2~0
CTRP2~CTRP0
: CTM CCRP 3-bit register, compared with the CTM counter bit 9 ~ bit 7
Comparator P match period=
000: 1024 CTM clocks
001: 128 CTM clocks
010: 256 CTM clocks
011: 384 CTM clocks
100: 512 CTM clocks
101: 640 CTM clocks
110: 768 CTM clocks
111: 896 CTM clocks
These three bits are used to setup the value on the internal CCRP 3-bit register, which
are then compared with the internal counter's highest three bits. The result of this
comparison can be selected to clear the internal counter if the CTCCLR bit is set to
zero. Setting the CTCCLR bit to zero ensures that a compare match with the CCRP
values will reset the internal counter. As the CCRP bits are only compared with the
highest three counter bits, the compare values exist in 128 clock cycle multiples.
Clearing all three bits to zero is in effect allowing the counter to overflow at its
maximum value.
• CTMC1 Register
Bit
7
6
5
4
3
2
1
0
Name
CTM1
CTM0
CTIO1
CTIO0
CTOC
CTPOL
CTDPX CTCCLR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
CTM1~CTM0
: Select CTM Operating Mode
00: Compare Match Output Mode
01: Undefined
10: PWM Output Mode
11: Timer/Counter Mode
These bits setup the required operating mode for the CTM. To ensure reliable
operation the CTM should be switched off before any changes are made to the CTM1
and CTM0 bits. In the Timer/Counter Mode, the CTM output pin state is undefined.
Bit 5~4
CTIO1~CTIO0
: Select CTM external pin CTP function
Compare Match Output Mode
00: No change
01: Output low
10: Output high
11: Toggle output
PWM Output Mode
00: PWM output inactive state
01: PWM output active state
10: PWM output
11: Undefined
Timer/Counter Mode
Unused
These two bits are used to determine how the CTM external pin changes state when a
certain condition is reached. The function that these bits select depends upon in which
mode the CTM is running.
In the Compare Match Output Mode, the CTIO1 and CTIO0 bits determine how the
CTM output pin changes state when a compare match occurs from the Comparator A.
The CTM output pin can be setup to switch high, switch low or to toggle its present
state when a compare match occurs from the Comparator A. When the bits are both
zero, then no change will take place on the output. The initial value of the CTM output
pin should be setup using the CTOC bit in the CTMC1 register. Note that the output
level requested by the CTIO1 and CTIO0 bits must be different from the initial value
