Only one buffer output for each bit is active at any time; the
other two will be in the high impedance “off” state. All three
buffer outputs can also be “off” (for example, with the transmit-
ter “OFF” or with power level latch outputs inhibited). The
HIGH, MEDIUM, or LOW buffer output is selected by making
the “C” input for that buffer HIGH and leaving the others LOW.
For each power level (HIGH, MED, or LOW), all 12 buffer “C”
inputs are connected together, and these three common connec-
tion lines are the “address” lines. For example, the “High Power
Level” logic signal from power level latch U40 addresses all
“C” inputs for the High Power Level buffers U9, U10 and U11.
When this address is logic HIGH, the 12-bit BCD output is the
BCD data from the High Power up-down counters.
Figure P-6 shows the Controller output and Analog Input Board
digital power data input circuit for BCD Bit 1. Note that when-
ever all three buffers for a bit are in their “High Impedance”
state, the latch inputs on the Analog Input Board will be pulled
LOW by a resistor to ground. If the three multiplex address lines
are all LOW, the latch inputs are all zero.
P.6.15
“Data Strobe” Output and Delay (U13-8,
U62-10)
The “Data Strobe” signal strobes (clocks) the Power Control
data latches on the Analog Input Board. The data latches
“clock,” the new data, on a low-to-high transition of the data
strobe signal. Data strobe pulses are generated by:
a. “K1 Start Pulse” from U56-13. This is a 1.6 second logic
LOW pulse, and “data strobe” occurs at the end of this
pulse (at the end of the step-start cycle).
b. “Power Level Change” pulse from U57-8. This is a logic
LOW pulse, and “data strobe” occurs at the end of the
pulse.
c. Up/down counter Clock pulses from U1-3/8/11. The
up/down counter also counts on the rising pulse edge, so the
“Data Strobe” pulse is delayed approximately 100 micro-
seconds by R2-C119 before the rising pulse edge strobes the
data latches on the Analog Input Board.
The “Data Strobe” signal is delayed, to allow the up/down
counters time to operate before the power data latches on the
Analog Input Board are strobed. A 100 microsecond pulse delay
circuit is made up of R-C network R2-C119 and Schmitt trigger
U62-10/11.
When U13-8 is LOW, capacitor C119 discharges through R2
and inverting Schmitt trigger U62-10 is HIGH. When an input
to U13-8 goes LOW, U13-8 goes HIGH, and C119 charges
through R2. After about 100 microseconds, U62-10 goes from
HIGH to LOW.
P.6.16
Power Control Status Indicator Drivers
(U46, U47)
“Status Indicator” driver circuits are shown on sheet 3 of the
Controller Schematic, 843-5400-091, on the left side of the
sheet. Status indicator drive outputs are:
a. RAISE, LOWER, HIGH, MEDIUM, LOW status: Logic
HIGH inputs illuminate indicator lamps in the buttons on
the transmitter front panel.
b. RAISE, LOWER, HIGH, MEDIUM, LOW status: Pro-
vide logic signals to the External Interface for remote or
extended control panel indications.
c. HIGH and MEDIUM status outputs: Operate Modula-
tion Monitor Sample level relays on the Output Monitor
through the LED Board.
P.6.16.1
Logic Buffers
Integrated circuits U46 and U47 are logic level down converters,
used as buffers. For each status output, one buffer section drives
the External Interface through a current-limiting resistor, and a
second buffer section drives an indicator lamp circuit. For HIGH
and MEDIUM status, a third buffer output goes to the Output
Monitor through the LED Board.
P.6.16.2
Front Panel Indicator Lamp Drivers
Each indicator lamp in the front panel switch is connected
between sections of Q3 and Q6 and +15 Vdc on the Switch-
board/Meter Panel. When the transistor base is logic HIGH, the
transistor turns on and illuminates the indicator lamp.
P.6.17
Clock Inhibit Gate (U1-6)
Inputs to the Clock Inhibit Gate, U1-6, shown on sheet 3 of the
Controller schematic diagram, are the Clock signal at U1-5 from
the clock frequency divider and the “Release Inhibit-H” signal
at U1-4 from the turn-on/turn-off control circuits.
The Clock Inhibit gate prevents clock pulses from triggering the
up-down counters during the transmitter step-start cycle, so that
the “Raise” and “Lower” functions cannot operate. The “Re-
lease Inhibit-H” input is logic LOW during the step-start cycle
and forces the inhibit gate’s output to remain LOW.
P.6.18
Clock Frequency Divider and Delay (U24,
U38, and U50-4/10)
The clock frequency divider circuit is shown on sheet 1 of the
Controller schematic diagram.
When “Raise” and “Lower” command is used to change power,
the rate at which power changes must be slow enough so that
the operator can easily adjust power to the desired level, par-
ticularly when using remote control and remote power readout.
The clock frequency from the switch debounce oscillator is
divided by eight, using three flip-flop “divide by two” circuits,
to permit precise power adjustment.
P.6.18.1
Fast Power Set (S1)
A “Fast Power Set” momentary contact pushbutton switch, S1,
bypasses the divider circuit and allows power changes to be
made quickly.
P.6.18.2
Clock Pulse Delay
U50-10 drives the R/C circuit R40 and C759. This circuit and
Schmitt trigger U50-4 delay the clock pulses by approximately
500 microseconds to debounce the momentary pushbutton
switch S1.
Section P - Controller (A38)
Rev. S: 05-02-97
888-2297-002
P-13
WARNING: Disconnect primary power prior to servicing.
