The analog signal level at the board’s input is high so that any
noise pickup on interconnecting cables does not degrade the
signal-to-noise ratio. Inverting amplifier U28 has a gain of 0.5 to
provide the proper single level to the A/D chip input and also
provides isolation between the board’s input and the A/D chip.
A very small amount of signal from the big step sync circuit is
added to the input signal through R70 at the inverting input of
U28 (pin 2). When a big step occurs in the output the last-bit
uncertainty in the A/D conversion process could cause a transi-
tion back to the previous step. This will produce a “glitch” or
spike in the modulated output as the unwanted switching be-
tween big steps takes place. The small voltage from the big step
sync circuit forces the input higher, just enough to ensure the A/D
converter will not switch back to the previous step.
High-speed Schottky diodes (CR16, CR18) protect the A/D’s
(U1) input against overvoltages. Schottky diodes also have low
turn-on voltages, 0.5 Volts or less. CR16 prevents the voltage
level input from going negative. CR19 prevents the voltage level
from going higher than about +5 Volts since CR10 is a 4.7 Volt
zener diode.
K.3.4.2
Analog to Digital Converter (U1, DL1)
A 12-bit analog to digital converter AD1671 is used. Conversion
time of the AD1671 is less than 800 nanoseconds. The analog
input voltage range is 0 to +5 Volts. An input of 0 Volts gives a
digital output of “0000 0000 0000". An input of +5 Volts gives
an output of ”1111 1111 1111".
The analog signal that is going to be converted to digital goes
into the A/D chip at pin 23. The ENCODE pulse goes into the
A/D chip at pin 17 and tells the A/D to do a conversion.
The 12 A/D output data lines are at pins 2 through 13. Pin 2 is
the least significant binary bit (LSB) and pin 13 is the most
significant binary bit (MSB). Pin 16 is the DAV pin (data avail-
able pin). DAV is a negative pulse that indicates when a conver-
sion is complete and data is valid on the 12 output lines.
The DAV pulse goes into a 450 nanosecond delay chip, DL1.
This delay is used to make this A/D board (843-5100-094 Rev
A) compatible with the previous A/D board (843-4038-049 Rev
P). The old version of the A/D board used a slower A/D chip that
was taken out of production.
K.3.4.3
Digital Data Latches (U3, U4, DL3)
The negative pulse from DL1 also goes to a 60 nanosecond delay,
DL3. The output from DL3 is the LATCH STROBE pulse. The
rising edge of this pulse latches the digital audio information
from the A/D converter into U3 and U4.
The digital audio data from latches U3 and U4 also goes to two
digital to analog (D/A) converters. D/A U22 is part of the big
step sync circuit and D/A U8 is part of the reconstructed audio
circuit.
The negative pulse from DL1 goes to the input of U7 pin 1 and
is the signal DATA STROBE-L on J6-26. The signals on the J6
connector go to the Modulation Encoder board. The rising edge
of the DATA STROBE-L is used to transfer the bits from latches
U3 and U4 into latches on the Modulation Encoder board.
K.3.5
Error Detecting Circuits
There are circuits on the A/D board that determines if the clock
signal is being received and if the A/D converter is working
properly. The error detection circuits use three re-triggerable
monostable mulitvibrators, called one-shots. If an error is de-
tected the logic signal CONVERSION ERROR-L will go low
and clear the storage latches on the A/D board and the storage
latches on the Modulation Encoder board.
K.3.6
One-Shot Operation (U13, U14)
One-shots produce an output pulse each time a rising or falling
edge is detected on the input. Each one-shot has three inputs; A,
B and CLEAR. Each has two outputs; Q and QN (not-Q). There
is an RC network connected to each one-shot which determines
the length of the pulse.
The following table logic low will be 0 and logic high will be 1.
Up is the rising edge of a pulse and down is the falling edge. X
denotes that either a 0 or 1 may be present.
A
B
CLEAR
Q
0
up
1
pulse (pos.)
down
1
1
pulse
0
1
up
pulse
1
X
X
0
X
0
X
0
X
X
0
0
One-Shot Operation Table
Re-triggerable means that if an input trigger condition occurs
again during an output pulse, the R-C network will be reset and
the pulse will be extend for the R-C time constant.
K.3.6.1
Power Up Reset (C41, R16, U12-F)
When the +5 Volt supply first comes on, the signal POWER UP
RESET-L (TP2) will be low for about 5 milliseconds. This logic
low clears the error detection one-shots (U13, U14). The signal
CLEAR-L (TP17) will be low which will clear the A/D latches
(U3, U4). The signal DATA CLEAR-L (J6-28) will also be low
and will clear the latches on the Modulation Encoder board.
Setting all latches to zero for 5 milliseconds will allow time for
power supplies to reach full voltage before any PA modules are
turned on and will also remove any data that might be entered in
any latches by transients during power-up.
The +5 Volt supply initially comes on causing C41 to charge
through R16 and the voltage at the inverter Schmitt trigger U12-F
to increase from zero. When the voltage across C41 goes above
the threshold of the inverter, the output will go high.
If the +5 Volt supply voltage fails, C41 will discharge through
diode CR13. The signal POWER UP RESET-L will again be low.
K.3.6.2
Clock Error Detection Circuit (U14-A)
The clock frequency TP6 can be from 410 kHz to 820 kHz so the
period is 1.2 to 2.5 microseconds. This is the input to pin 2 of
one-shot U14-A. The output of the one-shot is labeled CLK
ERROR-L. The one-shot output pulse is 3.6 microseconds long.
As long as the clock pulses are present the one-shot continues to
DX-25U
K-2
888-2297-002
Rev. X: 05-13-98
WARNING: Disconnect primary power prior to servicing.
