P.5.1.3
INHIBIT:
The one-shot is INHIBITED if the “A” input is HIGH, or the
“CLEAR” input is LOW. The following conditions INHIBIT
U56A:
a. “A” input HIGH: U56-1 “A” input goes high when K2 is
latched. This prevents a power mode change from generating
a new turn-on pulse while the transmitter is operating.
b. “CLEAR” input LOW: Refer to the previous paragraph
for Fault conditions which cause a “Clear-L” input.
P.5.2
One-Shot Trigger and Operation During
Transmitter Turn-on
a. When a HIGH, MEDIUM or LOW command is latched
into U40, the “OFF” output U40-2 goes from HIGH to
LOW. If no faults are present, the “INHIBIT K2” signal
at gate U52-8 is HIGH, and the ”CLEAR” signal at gate
U53-11 is HIGH. The one-shot can trigger.
b. At the same time, a HIGH, MEDIUM or LOW command
is latched into power control mode latch U40, and the
corresponding output goes from logic LOW to logic
HIGH. The “INHIBIT K2” signal at inputs of power
control gates U39-6/8/11 is HIGH. One of the gate out-
puts goes HIGH, and one input to Turn-On Request gate
U52-12 goes HIGH. This generates a “TURN ON RE-
QUEST-H” logic HIGH signal.
c. Turn-on one-shot U56A triggers, and generates the 1.6
second turn-on pulse.
d. When K2 closes, about 1.1 seconds after the beginning of
the “Xmtr Turn-On Pulse,” its auxiliary contact closure
generates a “K2 Has Closed-H” signal, which forces
U56-1 “A” input HIGH. This inhibits the one-shot, so that
it cannot be triggered again.
P.5.2.1
Logic Levels At U56A Inputs and Outputs
When the transmitter is OFF, U56-1, U56-2 and U56-3 are all
LOW. When the transmitter is ON, these three inputs are all
HIGH.
P.5.2.2
Contact De-bounce And Logic Level Converter Cir-
cuits (Q10-8 and U59-6, Q10-14 and U59-4).
These circuits are both the same. The following description
describes the circuit for the “K1 Aux Contact” input.
When the auxiliary contact closes, +30 Vdc is applied to J7-15
and voltage divider R91 and R92. Diode CR16 protects the
transistor input, resistor R93 limits base current and C106
provides filtering.
Transistor Q10-8 is a logic level converter. When the K1 auxil-
iary contact is open, Q10 is OFF and the collector voltage is
approxi5 Vdc (logic HIGH). When K1 energizes, the
auxiliary contact is closed and Q10 is turned ON. The collector
(pin 8) voltage goes to approximately zero Volts (logic LOW).
Because of the capacitor on Q10-9, the waveform at the collec-
tor has a long “rise” and “fall” time. Schmitt trigger U59-6
provides an output with a short rise and fall time. The output of
U59-6 is logic LOW when the contactor is OFF, and logic HIGH
when the contactor is ON. This output is the “Underdrive Inhibit
B” signal which resets the “Underdrive Fault” detector. Refer
to Section Q, LED Board, for a description of Underdrive Fault
circuits. The output of U59-6 also drives the 0.3 second delay
circuit.
P.5.3
Delay Circuits: Description
P.5.3.1
0.3 Second Delay Timer: Delay On/fast Off (R96,
R97, C90, and CR18).
When the auxiliary contact of K1 closes, the delay circuit input
from U59-6 goes HIGH and capacitor C90 charges through
R96. Diode CR18 is reverse biased at this time. After approxi-
mately 300 milliseconds, the voltage across C90 triggers U59-1,
and U59-2 output goes LOW. This logic LOW is inverted at
U59-12.
This is the “Underdrive Inhibit A” signal which turns on the
detection circuit on the LED Board through OR gate U51-6. It
is at this time that Drive level begins to be measured, and if it
does not come up in a predetermined manner, a Type 2 Fault
will be generated.
When K1 opens again, U59-6 goes LOW and capacitor C90
discharges through diode CR18 and resistor R97 to quickly
“reset” the delay timer.
P.5.3.2
0.8 Second Delay Timer (R65, C94, U62-2/4).
When the 0.3 second delay circuit output at U59-12 goes HIGH,
capacitor C94 charges to +5 Vdc through R65. After approxi-
mately 0.8 seconds U62-2 goes LOW. The logic LOW is in-
verted at U62-4. The 0.3 second and 0.8 second delays add, so
that U62-4 generates a logic HIGH signal 1.1 seconds after K1
closes. This logic HIGH signal is an input to OR gate U51, so
that U51-3 goes HIGH to generate a “K1 has 1.1 second
delay-H” signal. This signal generates the K2 drive signal at
U53-6 and the “Release Inhibit-H” signal to allow raise/lower
functions to operate.
P.5.3.3
150 Millisecond Delay (R74, C108, and U59-10)
This delay circuit operation is the same as operation of the 0.8
second delay, except for the shorter R-C timer constant. This
delay starts when contactor K2 energizes to complete the step-
start sequence. At the end of this delay, the “PA TURN-OFF”
signal from gate U53-3 to the LED Board is released, allowing
the PA Modules to turn on.
P.5.4
PA Off And Overdrive Inhibit Gate U52-6
The output of U52-6 is HIGH only if all three inputs are LOW.
If any input goes HIGH, the output goes LOW. The inputs are:
a. Pin 3 is grounded, holding it LOW
b. When the transmitter is OFF, the “K2 is 150
millisecond delay” input to U52-4 is HIGH. This forces
the output LOW and provides “PA Off” and “Overdrive
Inhibit” outputs. These hold the PA off and inhibit Over-
drive Sensing and Air Flow fault circuits on the LED
Board.
c. When an OFF command, Type 1 Fault or Type 2 Fault
generates an “Inhibit K2” signal, U52-5 goes HIGH. This
forces the output LOW and provides early PA Off and
Overdrive Inhibit.
DX-25U
P-6
888-2297-002
Rev. S: 05-02-97
WARNING: Disconnect primary power prior to servicing.
