A “PA Turn Off-H” signal is generated by the Controller during
fault protection and when the transmitter is turned OFF. This
logic HIGH input to U13-1 from J4-39 will be inverted to a logic
LOW at U13-2. This will turn Q1 ON and apply a positive voltage
to Q7 through Q1 and R20.
Transistor Q7 is an N-channel depletion mode JFET switching
transistor. When the gate of Q7 approaches zero Volts it conducts
(turns ON) and the drain-source resistance becomes less than 80
Ohms. Transistor Q7 and R82 form a voltage divider, so when
Q7 is ON, it effectively shorts the (Audio + DC) signal at U4-3
to ground.
When the transmitter is turned ON, the “PA Turn Off-H” signal
goes to logic LOW and turns off Q1 through U13. The gate of
Q7 is pulled to -15 VDC by R25 which will turn it OFF. When
Q7 is OFF it is an open circuit and the (Audio + DC) signal is
applied to U4-3. During normal operation, Q1 is not conducting,
C46 is charged to -15 VDC through R45, and Q7 is OFF.
Transistor Q8 and R23 form a second JFET voltage divider with
R82. This circuit is in parallel with Q7. When Q8 is turned on,
the series resistor R23 will cause the (Audio + DC) signal at U4-3
to be attenuated, but not shorted to ground.
Transistor Q8 will conduct longer than Q7 due to the delay circuit
C86 and R49 on the U13-3 input. When the “PA Turn Off-H”
signal changes from HIGH to LOW, C86 discharges slowly
through R49, and keeps Q2 conducting. When the “PA Turn
Off-H” signal is generated, C86 charges quickly through CR20
to reset the circuit.
This allows the RF power to come up in a two-step sequence:
first to half power, then, after a 1.5 to 2 second delay, full power.
The delay minimizes stress on the power supply and will give
antenna system components time to “settle down” or cool after
an arc has occurred, i.e. the antenna ball gaps and/or guy wire
insulators.
J.2.9
Differential Amplifier/Inverter U4
The (Audio + DC) signal is applied to U4-6 and a small level 72
kHz “dither” signal is added at U4-5. The output of U4-7 is sent
to the LED Board. For a 60 kW power output with 100%
modulation, the (Audio + DC) signal at U4-7 will be a -2 VDC
level with a 3 Vp-p audio level. A very small 72 kHz “dither”
component will be riding on the audio.
J.2.9.1
Dither Oscillator U13, U19, U5)
The Analog to Digital (A/D) conversion process has an inherent
+/-1 digit uncertainty. As the analog input changes, there may be
some switching back and forth between two steps because of this
uncertainty. This can result in some low-level residual noise. The
“Dither” oscillator minimizes this residual noise by introducing
a small 72 kHz triangle wave on the signal. This frequency is
well above the audio frequency range, but low enough so that any
72 kHz sidebands are attenuated by the bandpass filter/output
network. The Dither Oscillator is made up of an integrator (U3)
and a square wave generator (differential amplifier U19).
J.2.9.1.1
Square Wave Generator U19
Differential amplifier U19 operates “open loop,” so its gain is
very high. Assuming no “Big Step Sync” input, inverting input
U19-2 is at zero Volts. If the voltage at the non-inverting input
U19-3 is slightly positive the output U19-6 will go to the +15 V
supply rail. If the voltage at U19-3 is slightly negative, the output
will go to the -15 V supply rail. The output of U19 is clamped
by zener diodes CR11 and CR12 to +6 Volts or -6 Volts (the 5.1
Volt zener voltage plus the 0.7 Volt forward junction drop of the
other diode).
J.2.9.1.2
Integrator U3
This voltage is applied to potentiometer R41 to the inverting
input of U3-2. When the input is +6 Volts the output of U3-6 will
ramp DOWN and when the input is -6 Volts, the output of U3
will begin ramping UP. The rate at which the output of U3
changes is determined by the R41-C62 time constant, so that
adjusting R41 will adjust the oscillator’s frequency.
The output of the Dither Oscillator at U3-6 and TP10, is a triangle
wave with an amplitude of 1 Vp-p and a frequency of 72 kHz.
Resistors R39-R40 form a voltage divider, with one end at either
+6 or -6 Volts (fixed by the zener diode voltages) and the other
end at the oscillator’s output voltage (a triangle wave varying
b1 and -1 Volt). The output at U13-6 will cause U19-6
to switch High and LOW which will, in turn, feed back to the
input of U3-2. A voltage divider formed by R42 and Dither Level
Adjust potentiometer R43 reduces the dither signal to a very low
level at TP9 and U4-5.
J.2.9.1.3
A/D Big Step Sync
The “Big Step Sync” signal from the Analot to Digital Converter
consists of a short pulse each time a “Big Step” occurs. The sync
pulses at TP11 are buffered in non-inverting amplifier U5. The
output of U5-1 feeds to U19-2 as synchronizing pulses. If the
dither signal is ramping UP when a “Big Step” is turned OFF the
“Big Step Sync” pulse will change the direction of the dither
signal so it ramps DOWN. If the dither signal is ramping DOWN
when a “Big Step” is turned ON, the sync pulse will cause the
dither signal to change and ramp UP.
J.2.10
-(Audio + DC) Sample To DC Regulator
The DC Regulator provides a Modulated B- “bias voltage” to the
PA Modules to compensate for changes in their turn-on or
turn-off times as the number of modules ON changes. The
“OFFSET” control R84 is used to adjust the amount of DC offset
to U5-6 which will change the -(Audio + DC) signal sent to the
DC Regulator.
J.2.11
Analog Input Board Power Supplies
Supply voltages to the Analog Input Board are +22 VDC and -22
VDC from the low voltage power supply. Voltage regulator U2
provides a -15 VDC output. Voltage regulator U1 pr15
VDC which is also regulated to +5 VDC by zener diode CR15.
The regulated supplies are fused by F2 and F3. The regulators
also provide “Supply Fault” outputs which feed through the
Controller to fault circuits on the LED Board.
Section J - Analog Input (A35)
888-2297-002
J-3
WARNING: Disconnect primary power prior to servicing.
