K.5.2.3.1
Troubleshooting the Frequency Divider
The Synchronous Binary Counter, U29, divides the input by four
at pin 14. In this circuit, this output is fed back to the clock input
to get the divide by 2 function.
To check operation of U29, turn the Power Amplifier stage
“OFF” by placing the PA OFF switch S5 on the Controller in the
OFF (UP) position.
Remove the jumper plug at P10, and use a dual-trace oscilloscope
to observe input and outputs from U29. The output at U29-14
should be TTL level logic pulses at one-fourth the input fre-
quency.
K.5.2.4
EOC-L FAULT
Use a dual trace oscilloscope to compare timing of signals at TP3
and TP5. If the EOC status output of U2 at TP5 is still HIGH
when the next START CONVERT pulse at TP3 occurs the
EOC-L signal at U13-4 will stay LOW. This would indicate a
fault in A/D converter IC U2.
K.5.2.5
POWER UP RESET-L FAULT
Measure the voltage at U12-13. There should be a +5 VDC signal
present when the Low Voltage is ON. If there is no +5 VDC signal
and the +5 VDC supply at TP15 measures correctly, capacitor
C41 may be faulty. If there is a +5 VDC signal at U12-13, but
TP1 is logic LOW, replace U12.
K.6
Technical Assistance
See Technical Assistance clause on back of title page.
K.7
Replaceable Parts Service
See Replaceable Parts Service clause on back of title page.
Component
Function/Description
DS1
illuminates when an A to D converter failure
occurs. This indication is also available on the
Status Indicator Panel and at the External
Interface
F1
Protects the +22 V supply from +15 V
regulator faults.
F2
Protects the +8 V supply from +5 V regulator
faults
F3
Protects the -22 V supply from -15 V regulator
faults
JP10
Selects division ratio for A/D sample ( divide
by 1, 2 or 3). Refer to schematic diagram or
Frequency Determined Components chart.
JP11
Enables RF sample phase correction circuit
when in position 1-2 and 3-4
R78
Adjust pulse width of ENCODE signal to the
A/D converter
R7
Compensates for voltage offset errors in the
A/D converter
S1
Frequency determined adjustment; adjusts RF
sample phase to switch PA Modules on or off
at the RF zero crossings
S2
Sections A and B are open in the DX 10
Section A is closed in the DX 25.
S2A and S2B are closed in the DX 50.
Table K-1. Analog to Digital Board A34
Controls and Indicators
Component
Function/Description
TP1
Audio + DC, analog signal that is converted
to digital in the A/D chip
TP2
POWER UP RESET-L, logic signal that’s
active low
TP3
ENCODE, logic signal that tells the A/D chip
to do a conversion
TP4
+15 V FAULT-L, 0 Volts when the +15 V is
not working
TP5
DAV, logic signal that’s low when the A/D
conversion is done
TP6
CLOCK, logic signal that is used to create
the ENCODE pulse
TP7
LATCH STROBE, logic signal that stores
data in latches U3 and U4
TP8
logic signal that’s low when A/D ERROR-L
or CLK ERROR-L is low
TP9
Unfiltered reconstructed audio signa
TP10
AA Ground (reconstructed audio signal
ground)
TP11
+ 5 V FAULT-L, 0 Volts when the + 5 V is
not working
TP12
-15 V regulator output
TP13
+15 V regulator output
TP14
-15 V FAULT-L, -20 Volts when the -15 V is
not working
TP15
+5 V regulator output
TP16
B Ground (analog ground)
TP17
CLEAR-L, logic signal that’s active low
TP18
B Ground (analog ground)
TP19
A Ground (digital ground)
TP20
A Ground (digital ground)
TP21
A Ground (digital ground)
TP22
-5V regulator output
Table K-2. Analog to Digital Board A34
Test Points
Section K - Analog to Digital Converter (A34)
Rev. X: 05-13-98
888-2297-002
K-5
WARNING: Disconnect primary power prior to servicing.
