count “up” input of the next counter. For the “one’s” counter,
the carry increments the “ten’s” counter one digit; the “ten’s”
carry output increments the “hundred’s” counter.
P.6.10.3
“Borrow”
When counting DOWN, each counter generates a “Borrow”
output when it goes from “0” to “9”. The “borrow” output goes
to the next counter’s count “Down” input so that the next counter
counts “down” one digit.
P.6.10.4
Up-down Counter “Clock”
The counters count up or down when a low-to-high logic
TRANSITION occurs at one of the clock inputs.
The Clock input for the counters is from the “Switch Debounce”
IC, U45. The 200 Hz clock frequency is divided down to 24 Hz,
by U38 and U24. The lower clock frequency changes power
slowly enough for accurate adjustment.
P.6.10.5
Power Control Data “Memory”
As long as supply voltage is present, the outputs of the up/down
counters do not change unless the clock is applied. The supply
voltage for the counters is from the +5B backup supply, so that
the power control data is “remembered” when primary AC is
removed.
P.6.10.6
Power Control “Clear”
Each counter has a CLEAR input. When the CLEAR input is
HIGH, the BCD output goes to “000.” If the +5B backup power
supply voltage goes too low for reliable counter or memory opera-
tion, the +5B Reset circuit generates a logic HIGH signal which
resets the counters. The counters can operate at a supply voltage as
low as +2 Vdc. The +5B Reset signal is generated when the backup
supply voltage drops to approxi3.1 Vdc.
P.6.11
Up-Down Counter Control Gates (U1, U2,
U14, U26)
Up-down counter control gates route the clock pulse to the
proper counter input, depending on which Power Level has been
selected and whether “Raise” or “Lower” is active. There are six
gates, one for each counter input, as follows:
a. U2-6: High Power level RAISE (count up)
b. U2-8: High Power level LOWER (count down)
c. U14-6: Medium Power level RAISE (count up)
d. U14-8: Medium Power level LOWER (count down)
e. U26-6: Low Power level RAISE (count up)
f. U26-8: Low Power level LOWER (count down)
The counter control gates are four-input NAND gates. Each gate
output is LOW only if all four inputs are HIGH. The output is
forced HIGH if any one or more inputs are LOW. All inputs are
labeled on the Controller Schematic diagram.
P.6.11.1
Gate Inputs
The four inputs to each counter control gate are:
a. CLOCK pulse
b. RAISE-H or LOWER-H logic signal.
c. HIGH, MEDIUM, or LOW power level select signal
d. INHIBIT signal
The clock pulse train alternates between HIGH and LOW states.
Clock pulses will appear at a gate’s output only when:
a. The Inhibit-L input is HIGH
b. The Raise or Lower input is HIGH
c. The power level select input is HIGH
d. The transmitter is ON
P.6.12
Data Strobe Gates (U1-3/8/11 and U13-8)
Whenever an up-down counter is counting, each clock pulse
generates a “Data Strobe” signal for the power control data
latches on the Analog Input Board. Clock pulses for each power
level are applied to three sections of U1. The outputs of these
three gates feed U13-1/4. The output of U13-8 is delayed and
inverted at U62-10 to form the Data Strobe signal.
P.6.13
Up-Down Counter “Inhibit” Circuits
Inhibit circuits stop counter operation at “000” and “999”. The
“LO” circuits generate a logic LOW inhibit when counter output
reaches “000.” The “HI” circuits generate a logic LOW inhibit
when counter output reaches “999”. Inhibit circuits include the
following:
a. HI-HI circuit: U3
b. HI-LO circuit: U5, U4, U25-6
c. MED-HI circuit: U15
d. MED-LO circuit: U17, U16, U25-4
e. LOW-HI circuit: U36
f. LOW-LO circuit: U34, U35, U25-2.
P.6.13.1
HI-LO, MED-LO, and LO-LO Inhibit
The “LO” inhibit is easiest to understand. Zero power is decimal
“000” or BCD “0000/0000/0000”; all bits are zero (logic LOW).
For any other power, at least one the 12 BCD bits will be one
(logic HIGH). A logic LOW inhibit signal must be generated
when all bits are zero. The “LO” inhibit must be LOW when all
binary bits are zero, otherwise the output must be logic HIGH.
The “HI-LO” inhibit circuit (U5, U4 and U25) will be used as
an example; the “MED-LO” and “LO-LO” inhibit circuits are
the same. Each bit of the 12 bit BCD signal goes to inverter U5
or U4. All inverters have open-collector outputs, and all 12
outputs go to the input of inverter U25-5. Resistor R13 pulls
U25-5 HIGH if all 12 inverter inputs are LOW. This will cause
U25-6 to go LOW and inhibit U2. When any of the 12 inverter
inputs are HIGH, U25-5 will be pulled LOW and U25-6 will go
HIGH to enable U2.
P.6.13.2
HI-HI, MED-HI, and LOW-HI Inhibit
The “HI” Inhibit must generate a logic LOW signal when the
BCD output is “999”. To understand these circuits examine the
Binary Coded Decimal numbers below:
0 = 00005 = 0101
1 = 00016 = 0110
2 = 00107 = 0111
3 = 00118 = 1000
4 = 01009 = 1001
Section P - Controller (A38)
Rev. S: 05-02-97
888-2297-002
P-11
WARNING: Disconnect primary power prior to servicing.
